Delay Models

Transport delay:

models the current flow through a wire (everything is transferred)

Transport Delay

Inertial delay: (default delay mechanism)

models spike-proof behavior ➔ a value is transferred only if it is active for at least 2 ns

Inertial Delay

Inertial delay with pulse rejection limit:

models spike-proof behavior ➔ a value is transferred only of it is active for least 5 ns

Inertial delay with pulse rejection limit

Notes

There are two different delay models in VHDL: transport and inertial, which is used per default.

In the transport delay model, everything is transferred via the signal, as can be seen in the upper example: signal A is an exact copy of signal S, delayed by 2 ns.

Transport delay models signal transfers by wire with pure propagation delay, thus spikes are not filtered out.

When using inertial delay, signal transitions are only transferred when the new value remains constant for a minimum amount of time, thus spikes are suppressed.

“S ⇐ A after 2 ns” filters out all spikes of less than 2 ns and delays signal values which remain constant for a longer period of time for 2 ns.

“Reject Inertial” delay:

“S ⇐ reject 5 ns inertial A after 10 ns” requires a minimum pulse width of 5 ns and copies all other signal values from A to S with 10 ns delay.

Inertial delay is characteristic of switching circuits. Spikes which are shorter than the necessary specific switching time of the circuit have no effect on the succeeding switch and will not be transmitted.

Transport and inertial delay:
1. All old transactions, that are projected to occur at or after the time at which the earliest new transaction is projected to occur, are deleted from the projected output waveform.
2. The new transactions are then appended to the projected output waveform in the order of their projected occurrence.
For inertial delay projected output waveform is further modified:
1. All of the new transactions are marked.
2. An old transaction is marked if the time at which it is projected to occur is less than the time at which the first new transaction is projected to occur minus the pulse rejection limit.
3. For each remaining unmarked, old transaction, the old transaction is marked if it immediately precedes a marked transaction and its value component is the same as that of the marked transaction
4. The transaction that determines the current value of the driver is marked.
5. All unmarked transactions (all of which are old transactions) are deleted from the projected output waveform.

Notes

The definition of the delay mechanism is quoted from the VHDL language reference manual.

As conclusion, all signal assignments can be brought into the following format:

T <= reject TIME_1 inertial VALUE after TIME_2;

The following assignments are equivalent:

T <=                        VALUE after TIME_1; -- (default inertial delay) 
T <= inertial               VALUE after TIME_1; 
T <= reject TIME_1 inertial VALUE after TIME_1;

Also equivalent are:

T <= transport VALUE after TIME_1; 
T <= reject 0 ns inertial VALUE after TIME_1;

This is because a pulse rejection limit of 0 ns makes all transaction being marked (step 3) and thus none of the transactions will be deleted in step 7. Consequently steps 3 to 7 have no effect and the delay model is actually equivalent to transport delay.

Furthermore “T ⇐ VALUE” is just a shortcut for “T ⇐ VALUE after 0 ns”.

signal S : integer := 0;
process
begin
       S <= transport 1 after 1 ns; -- both
       S <= transport 2 after 2 ns; -- remain
       wait;
end process;

signal S : integer := 0;
process
begin
       S <= transport 2 after 2 ns; -- gets lost
       S <= transport 1 after 1 ns; -- wins
       wait;
end process;

A signal driver manages value/time pairs

Notes

Within a signal driver, the actual values are always associated with an activation time. The initial value/time (0, 0 ns) pair for the integer signal of the example is left out in the figures as this pair remains unaffected at any time.

Whenever a signal assignments leads to a new pair, it must be decided, whether the time in the value/time pair is chronologically after the time of the last list entry or not. The first signal assignment is the most simple one as it is just appended to the list. The same applies to pairs that occur later on in time (left example; step 2). Otherwise the new value/time pair will be inserted chronologically after the pair with the next previous time specification and all succeeding pairs will be deleted (right example; step 1).

It is not possible to insert a new value/time pair before an already existing one without deleting all succeeding pairs!

signal S : integer := 0;
process
begin
       S <= transport 1 after 1 ns;
                      3 after 3 ns;
                      5 after 5 ns;
       S <= transport 4 after 4 ns;
       wait;
end process;

signal S : integer := 0;
process
begin
       S <= transport 1 after 1 ns;
                      3 after 3 ns;
                      5 after 5 ns;
       S <= transport 4 after 6 ns;
       wait;
end process;

New pairs are either appended to the list overwrite the remaining elements

Notes

After the first signal assignment the driver of S contains three value/time pairs.

The signal assignment occurring after 4 ns (left example: “S ⇐ transport 4 after 4 ns”) is prior to the last assignment that was specified before. Thus, the last entry is overwritten: In step 1, the last list element is deleted; in step 2, the new pair is added. If the list had been longer, then the following list entries would have been deleted too.

In the second example (“S ⇐ transport 4 after 6 ns”), the pair is attached to the list, because the time entry of this pair follows chronologically the time entry of the last list element (nothing to do in step 1, only step 2). The time entry t i of the additional value/time pair decides on whether the list is overwritten and the following entries have to be deleted (t i-1 >= ti), or whether the pair will be attached to the list (t i-1 < ti).

signal S : 
   integer := 0;
process
begin
  S <= 1 after 1 ns;
  S <= 2 after 2 ns;
  wait;
end process;

signal S : 
   integer := 0;
process
begin
  S <= 1;
  S <= 2;
  wait;
end process;

signal S : 
   integer := 0;
process
begin
  S <= 2 after 2 ns;
  S <= 1 after 1 ns;
  wait;
end process;

signal S : 
   integer := 0;
process
begin
  S <= 1 after 2 ns; -- overwritten
  S <= 1 after 1 ns; -- remains
  wait;
end process;

-- S <= 1; equivalent to S <= 1 after 0 ns;

The last assignment to a signal in a process takes effect

Notes

In the left example, the pulse rejection limit of the signal assignment “S ⇐ 2 after 2 ns” equals 2 ns. Therefore, all transactions are marked, whose recurrence time is smaller than 0 ns (2 ns minus pulse rejection time; step 4). Accordingly the pair (1, 1 ns) is not marked and deleted in the final step (step 7).

The time in the new value/time pair in the three right hand side examples is at most as big as the time of the pair in the list, thus the old entry is overwritten by the new one (step 1 deletes, step 2 adds new pair), independent from rejection limit values.

Chapters of System Design > Simulation

Delay Models

Types of Delay

Notes

Projected Output Waveforms (LRM)

Notes

Transport Delay (1)

Notes

Transport Delay (2)

Notes

Inertial Delay

Notes

VHDL-Online