Testbenches

after “Fundamentals”:

Empty entity

entity TB_TEST is
end TB_TEST;

Declaration of the DUT
Connection of the DUT with testbench signals
Stimuli and clock generation (behavioural modelling)
Response analysis

architecture BEH of TB_TEST is
   -- component declaration of the DUT
   -- internal signal definition
begin
   -- component instantiation of the DUT
   -- clock generation
   -- stimuli generation
end BEH;

default or customized configuration to simulate the testbench

configuration CFG_TB_TEST of TB_TEST is
   for BEH;
       -- customized configuration
   end for;
end CFG_TB_TEST;

Notes

The entity of a testbench is completely empty, because all necessary stimuli are created standalone. Otherwise a testbench for the testbench would be needed. As the DUT's inputs cannot be stimulated directly, internal temporary signals have to be defined. In order to distinguish between port names and internal signals, prefixes can be employed, for instance “W_” to indicate a wire.

The declaration part of the testbench's architecture consists of the definition of the internal signals, a component declaration of the DUT or DUTs and perhaps some constant definitions e.g to set the clock period duration. A stimuli process provides the values for the DUT's input ports, in which behavioural modelling can be employed as there is no need to synthesize it. Sometimes, models of external components are available (probably behavioural description, only) and can be used similar to create a whole system.

A configuration is used to pick the desired components for the simulation.

signal S : integer := 0;
process
begin
  S <= 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;
  S <= 3 after 4 ns; 4 after 5ns;
  wait;
end process;

Starting waveform in ascending order

Starting Waveform in ascending order

S <=  1 after 1 ns, 3 after 3 ns, 5 after 5 ns;

signal S : integer := 0;
process
begin
  S <= 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;
  S <= 3 after 4 ns; 4 after 5ns;
  wait;
end process;

Resulting waveform in ascending order

S <=  3 after 4 ns, 4 after 5 ns;

Notes

After the first signal assignment “S ⇐ 1 after 1 ns, 3 after 3 ns, 5 after 5 ns;” the list contains three value/time pairs.

The second signal assignment “S ⇐ 3 after 4 ns, 4 after 5 ns;” deletes the last entry from the list because 4 ns ⇐ 5 ns (step 1) and appends two entries (step 2). Then, all new transactions (step 3) and also (3, 3 ns) will be marked, because this transaction is a direct predecessor of a marked transaction and it has the same value as this marked transaction, namely 3 (step 5). The unmarked entries will be deleted, that is the pair (1, 1 ns) and (2, 2 ns) in the second case respectively (step 7).

signal S : integer := 0;
process
begin
  S <= 2 after 3 ns, 2 after 12 ns, 12 after 13 ns, 5 after 20 ns,
       8 after 42 ns;
  S <= reject 15 ns inertial 12 after 20 ns, 18 after 41 ns;
  wait;
end process;

Intertial Delay Waveform

Notes

The signal assignment “S ⇐ 2after3ns, 2after12ns, 12after13ns, 5after20ns, 8after42ns;” builds the first list. The second signal assignment “S ⇐ reject 15 ns inertial 12 after 20 ns, 18 after 41 ns;” modifies this list in the following way:

step 1 : all pairs with time values greater than or equal to 20 ns will be removed
step 2 : the new pairs will be attached
step 3 : all new transactions will be marked (light gray);
step 4 : old transactions with a time value smaller than the time value of the first new transaction (20 ns) minus the reject limit (15 ns), i.e. 5 ns, will be marked (dark gray)
step 5 : still unmarked transactions will be marked (gray), if they are direct predecessor of a marked transaction and contain the same value as the already marked transaction
step 6 : the current value/time pair will be marked; as this pair has to be marked anyway it is not displayed in the list
step 7 : all unmarked transactions will be deleted

Chapters of System Design > Simulation

Testbenches

Structure of a VHDL Testbench

Notes

Delay Models

Inertial Delay (2)

Notes

Inertial Delay (3)

Notes

VHDL-Online