REGISTERs library
The REGISTERs library consists of the following 1 generic component:
- reg_P_X_Y: N-read port register file with X words of Y bits each
The REGISTERs library can be verified with this testbench: test_registers
reg_P_X_Y
- registers.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : registers.vhd # -- # # -- # Component : reg_P_X_Y : P-read-port reg. file with X words of Y bit. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; --**************************** -- reg_P_X_Y Entity Description* --**************************** entity reg_P_X_Y IS GENERIC( p : INTEGER := 1; x : INTEGER := 4; y : INTEGER := 4 ); PORT( DIN: IN STD_ULOGIC_VECTOR (y-1 DOWNTO 0); DOUT: OUT stdv_2d (p-1 DOWNTO 0,y-1 DOWNTO 0); RADR: IN stdv_2d (p-1 DOWNTO 0,log2(x)-1 DOWNTO 0); WADR: IN STD_ULOGIC_VECTOR(log2(x)-1 DOWNTO 0); LD,WE: IN STD_ULOGIC ); END reg_P_X_Y; --********************************** -- rgp_x_y Architecture Description* --********************************** ARCHITECTURE rtl OF reg_P_X_Y IS SUBTYPE ramword IS std_ulogic_vector (y-1 DOWNTO 0); TYPE rammemory IS ARRAY (x-1 DOWNTO 0) of ramword; SIGNAL ram : rammemory; BEGIN REGISTER_FILE_read_Process: process(ram,RADR) variable temp1 : std_ulogic_vector (y-1 DOWNTO 0); variable temp : std_ulogic_vector (log2(x)-1 DOWNTO 0); BEGIN FOR i IN p-1 DOWNTO 0 LOOP FOR j IN log2(x)-1 DOWNTO 0 LOOP temp(j) := RADR(i,j); END LOOP; temp1 := ram(to_Integer('0' & temp (log2(x)-1 DOWNTO 0))); FOR k IN y-1 DOWNTO 0 LOOP DOUT(i,k) <= temp1(k); END loop; END loop; END PROCESS REGISTER_FILE_read_Process; REGISTER_FILE_write_Process: process(DIN,WE,LD,WADR) variable waddr : integer range 0 to x; variable load : std_ulogic; BEGIN -- write mode? (need both WE1 and LD1 to be high) -- convert address to integer waddr := to_Integer('0' & WADR,0); load := LD and WE; if (load = '1') then ram(waddr) <= DIN; end if; END PROCESS REGISTER_FILE_write_Process; end rtl;
Testbench
- test_registers.vhd
-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_registers.vhd # -- # # -- # Component : test_reg_P_X_Y : Test Bench for an P-read-port reg. file # -- # with X words of Y bit. # -- # # -- # Model : rtl # -- # # -- # Designer : S. Theoharis,N. Zervas # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use work.useful_functions.all; ENTITY test_registers IS END test_registers; ARCHITECTURE rtl OF test_registers IS COMPONENT rg2_4_8 GENERIC(p : INTEGER := 1; x : INTEGER := 4; y : INTEGER := 4 ); PORT( DIN: IN std_ulogic_vector (y-1 DOWNTO 0); RADR: IN stdv_2d (p-1 DOWNTO 0,log2(x)-1 DOWNTO 0); WADR: IN std_ulogic_vector(log2(x)-1 DOWNTO 0); DOUT: OUT stdv_2d (p-1 DOWNTO 0,y-1 DOWNTO 0); LD,WE: IN std_ulogic ); END COMPONENT; FOR mem : rg2_4_8 USE ENTITY WORK.reg_P_X_Y(rtl); SIGNAL DIN: std_ulogic_vector (7 DOWNTO 0); SIGNAL RADR: stdv_2d (1 DOWNTO 0,log2(4)-1 DOWNTO 0); SIGNAL DOUT: stdv_2d (1 DOWNTO 0,7 DOWNTO 0); SIGNAL WADR: std_ulogic_vector(log2(4)-1 DOWNTO 0); SIGNAL LD,WE: std_ulogic; BEGIN mem: rg2_4_8 GENERIC MAP(p => 2, x => 4, y => 8) port map( DIN => DIN, RADR => RADR, DOUT => DOUT, WADR => WADR, LD => LD, WE => WE); LD <= '1' AFTER 0 ns, '0' AFTER 0350 ns; WE <= '1' AFTER 0 ns, '0' AFTER 0350 ns; WADR <="11" AFTER 0 ns, "10" AFTER 0200 ns, "01" AFTER 0250 ns, "00" AFTER 0300 ns, "ZZ" AFTER 0350 ns; RADR <= ("00","11") AFTER 0 ns, ("10","10") AFTER 0450 ns; DIN <= "01010101" AFTER 0 ns, "11111111" AFTER 200 ns, "00000000" AFTER 250 ns, "00001111" AFTER 300 ns, "ZZZZZZZZ" AFTER 350 ns; END rtl;