courses:system_design:vhdl_-_overview_and_application_field:vhdl_-_overview_and_history

VHDL - Overview and History

  • VHSIC (Very High Speed Integrated Circuit) Hardware Description Language
    • Modeling of digital systems
    • Concurrent and sequential statements
    • Machine-readable specification
    • Design lifetime > designer lifetime
    • Man- and machine-readable documentation
  • International Standards:
    • IEEE Std 1076-1987 (VHDL-87)
    • IEEE Std 1076-1993 (VHDL-93)
  • Analogue- and Mixed-Signal extension:
    • IEEE Std 1076.1-1999 (VHDL-AMS)
  • Pure definition of language in the LRM (Language Reference Manual)
    • No standards for application or methodology

Notes

VHDL development was initiated originally from the American Department of Defense (DoD). They requested a language for describing a hardware, which had to be readable for machines and humans at the same time and strictly forces the developer to write structured and comprehensible code, so that the source code itself can serve as a kind of specification document. Most important was the concept of concurrency to cope with the parallelism of digital hardware. Sequential statements to model very complex functions in a compact form were also allowed.

In 1987, VHDL was standardized by the american Institute of Electrical and Electronics Engineers (IEEE) for the first time with the first official update in 1993. Apart from the file handling procedures these two versions of the standard are compatible. The standard of the language is described in the Language Reference Manual (LRM).

A new and difficult stage was entered with the effort to upgrade VHDL with analogue and mixed-signal language elements. The upgrade is called VHDL-AMS (analogue-mixed-signal) and it is a superset of VHDL. The digital mechanisms and methods have not been altered by the extension.

Actually, only simulation is feasible for the analogue part because analogue synthesis is a very complex problem affected by many restrictions and constraints. The mixed signal simulation has to deal with the problems of synchronizing the digital- and analogue simulators and finding solution algorithms for all kinds of nonlinear differential equations.

  • early ’70s - Initial discussions (idea: document behavior of ASICs)
  • late ’70s - Definition of requirements
  • 1982 - Contract of development with IBM, Intermetrics and TI
  • 1984 - Version 7.2
  • 1986 - IEEE-Standard
  • 1987 - DoD adopts the standard → IEEE 1076-1987 (VHDL-87)
  • 1988 - Increasing support by CAE manufacturers
  • 1991 - Revision
  • 1993 - New Standard (VHDL-93)
  • 1999 - VHDL-AMS extension (IEEE 1076.1)
  • 2006 - Draft 3.0 of VHDL-2006 (inkl. extension, PSL, C/C++ interface)
  • 2008 - VHDL standard IEEE 1076-2008 (VHDL-2008) - addr. 90 issues: enhanced generic types, process(all), fixed/floating-point pkgs…

Notes

VHDL is a language which is permanently extended and revised. The original standard itself needed more than 16 years from the initial concept to the final, official IEEE (Institute of Electrical and Electronics Engineers) standard. When the document passed the committee it was agreed that the standard should be revised every 5 years. The first revision phase resulted in the updated standard of the year 1993.

Independently of this revision agreement, additional effort is made to standardize “extensions” of the pure language reference. These extensions cover for examples packages (std_logic_1164, numeric_bit, numeric_std, …) containing widely needed data types and subprograms, or the definition of special VHDL subsets like the synthesis subset IEEE 1076.6.

The latest extension is the addition of analogue description mechanisms to the standard which results in a VHDL superset called VHDL-AMS.

In February 2008, Accellera (IEEE working group) approved VHDL 4.0 also informally known as VHDL 2008. In this class we refer to VHDL87 and 93, for this actually is industry standard.

  • Hardware design
    • ASIC: technology mapping
    • FPGA: CLB mapping
    • PLD: smaller structures, hardly any use of VHDL
    • Standard solutions, models, behavioral description,..
  • Software design
    • VHDL – C interface (tool-specific)
    • Main focus of research (hardware/software co-design)

Notes

VHDL is used mainly for the development of Application Specific Integrated Circuits (ASICs). Tools for the automatic transformation of VHDL code into a gate-level netlist were developed already in the early 1960s. This transformation is called synthesis and is an integral part of current design flows.

In the first step, boolean equations are derived from the VHDL description, no matter, whether an ASIC or a FPGA is the target technology. But now, this boolean code has to be partitioned into the configurable logic blocks (CLB) of the FPGA. This is more difficult than the mapping onto an ASIC library. Another big problem is the routing of the CLBs as the available resources for interconnections are the bottleneck of current FPGAs.

While synthesis tools cope pretty well with complex designs, they obtain usually only suboptimal results. Therefore, VHDL is hardly used for the design of low complexity Programmable Logic Devices (PLDs). VHDL can be applied to model system behavior independently from the target technology. This is either useful to provide standard solutions, e.g. for micro controllers, error correction (de-)coders, etc., or behavioral models of microprocessors and RAM devices are used to simulate a new device in its target environment.

An ongoing field of research is the hardware/software codesign. The most interesting question is which part of the system should be implemented in software and which part in hardware. The decisive constraints are the costs and the resulting performance.

ASIC Development

Notes

The development of VHDL models starts with their specification which covers functional aspects and the timing behavior. Sometimes a behavioral VHDL model is derived from there, yet synthesizable code is frequently requested right from the beginning. VHDL code can be simulated and checked for the proper functionality.

If the model shows the desired behavior, the VHDL description will be synthesized. A synthesis tool selects the appropriate gates and flip-flops from the specified ASIC library in order to reproduce the functional description. It is essential for the synthesis procedure that the sum of the resulting gate delays along the longest paths (from the output to the input of every Flip Flop) is less than the clock period.

As soon as a model built of ASIC library elements is available, a simulation on gate level can be performed. Now gate and propagation delays have to be taken into account. Delay values can be included in each VHDL model description, i.e. the designer receives the first clues about maximum clock frequency and critical paths after synthesis, already.

The propagation delay along the signal wires have to be estimated first because the actual values are available after the layout is finished. The process of feeding these values back into the VHDL model is called back annotation. Once again it must be checked, whether the circuit fulfils the specified timing constraints.


Chapters of System Design > VHDL - Overview and Application Field