Table of Contents

VHDL Workshop: Camera

Introduction

This VHDL teaching program is divided into several exercises. By writing typical VHDL programs you learn how to use this hardware description language. In the beginning you are guided in a step by step manner, later on when you are used to the language and the tools you will solve the tasks on your own. We are referring to the VHDL’87 standard, because the VHDL’93 is not yet supported by all tool manufacturers.

Structure of the Exercises

The tasks are divided into different sections:

Style Guide

In VHDL it is very important to have a consistent naming. The following naming conventions should be followed within this workshop:

File name: mydesign.vhd for the VHDL file
Entity name: MYDESIGN
TB_MYDESIGN 		for the model
for the testbench
Architecture name: RTL
TEST 		for RTL code
for the architecture of the testbench
Configuration name: CFG_TB_MYDESIGN for the configuration of the testbench
Type definition name: T_<TYPE_NAME> a leading T_ …

Design Structure

The goal of this course is the design of a camera control system. Its main focus is to demonstrate the application of the hardware description language VHDL in a real world setting. Of course, the problem has been heavily simplified, yet it is powerful enough to point out all main concepts of the language to the beginner. After completing the course you should feel comfortable writing VHDL code on your own.

The camera control system has to generate the appropriate signals for the lens shutter and the film transportation motor. It also generates the input signals for a small 7-segment display showing either the current exposure time or the total number of pictures taken so far. The user controls the camera operation via several keys.

Modules of the camera system

The central control system that is to be developed in this course is split into seven modules:

  1. A decoder (decoder) is used to preprocess the signals from the input device for the controller.
  2. The exposure latch (exp_ff) stores the selected exposure time.
  3. A timer for the film transport (motor_timer) is used to detect errors during film transportation, e.g. if the film is torn apart.
  4. The exposure controller (exp_ctrl) opens the lens shutter for the selected exposure time and counts the number pictures that have been taken.
  5. The photo controller (main_ctrl) is the central control unit for the camera control system.
  6. A specialized display controller (disp_ctrl) selects the appropriate data for the 7-segment display.
  7. The display driver (disp_drv), finally, converts the internal data signals into a format suitable for the output device.

The clock frequency of the camera control is 8192 Hz. It allows for exposure times according to the following formula: 

2^(-i) seconds (for i = 0..9).

You need this information later on in order to implement the required times. The camera control system has to:

VHDL Working Environment

In order to follow the exercises you will need an editor to enter the code. It is advisable to use an editor with a VHDL language mode as they facilitate the detection of typographic errors in VHDL keywords. The notorious Emacs disposes of a powerful VHDL macro set with templates for most language constructs, special copy & paste functions for signal lists and much more.

As the VHDL simulators can not deal with ASCII text immediately, your designs need to be compiled into a machine readable format first. After the proper behaviour has been verified, a synthesis tool is used to map the RTL description to a network of gates. In addition to the software package you will also need a library containing a description of the properties of all available cells.

The goal of this pre-exercise is to get used to the simulation and synthesis tools, and to learn the basic commands of the tools used. As there is a great variety of tools we can give only very generally descriptions of the tasks to do. This exercise does not require any specific VHDL knowledge. In order to get used to the tools, please refer to the corresponding user manuals of the software tools used and proceed through the following steps:

Directory Structure

First, you will need a directory where you can store the VHDL source code files. In the following, we assume that ~/workshop is the base directory for this project. It is advisable to separate the VHDL sources from their derived files, i.e. we will create a subdirectory ~/workshop/WORK for the analysed objects.

Working Environment

The simulation and synthesis software can have their own setup files. Especially if You are using tools from different producers. The principles for initializing the software are quite often similar. Please consult your software documentation for detailed information.

Simulation Setup

Normally a setup file has to be created. You can do this either by hand with an editor (save the file in the current, it is the ~/workshop directory) or within a menu of the software used.

Example of a simulation setup file:

.synopsys_vss.setup
TIMEBASE = NS
 
WORK    >  DEFAULT
DEFAULT :  ./WORK
 
USE = .

Synthesis Setup

Normally a setup file has to be created. You can do this either by hand with an editor (save the file in the current, it is the ~/workshop directory) or within a menu of the software used. If you use a framework perhaps only one setup file for simulation and synthesis is needed.

Example of synthesis setup file:

.synopsys_dc.setup
search_path = search_path + { . }
 
define_design_lib work -path ./WORK
 
link_path = {vendorlib.db }
target_library = {vendorlib.db }
symbol_library = {vendorlib.sdb }
link_library = {vendorlib.db }

VHDL Code

The design flow that will be followed throughout the exercises will be demonstrated at the example of a simple AND-gate. Please create a file named and_gate.vhd in your VHDL sources directory (~/workshop) and enter the following code.

and_gate.vhd
-- VHDL model of an AND gate
library IEEE;
use IEEE.std_logic_1164.all;
 
entity AND_GATE is
port (A,B : in std_logic;
        Z : out std_logic);
end AND_GATE;
 
architecture RTL of AND_GATE is
begin
  Z <= A and B;
end RTL;

VHDL Compiler

Before you will be able to simulate the design you have to compile your ASCII sources. An so called analyser (sometimes also called “compiler”, “reader”, …) is used for this purpose. The resulting files are stored in the default library which is mapped to the directory ./WORK in the simulation setup file. If you need to compile your sources into a different library, please refer to the corresponding user manual. Of course, the other library has to be mapped to a physical directory, as well.

Please remember that the VHDL design units have to be analysed in a certain order. You (sometimes the software will do this for you) will have to observe the following rules in order to avoid compilation errors:

The referenced standard package std_logic_1164 is already available in compiled format, i.e. you just have to analyse the entity AND_GATE before its RTL architecture. As the entity description is located in front of the architecture definition in the source code, please just compile this file and you will be ready to simulate the design.

VHDL Simulator

In order to verify the proper behaviour of your VHDL code, you will also need to create testbenches that stimulate your design. The testbench for the AND gate contains the instantiation of the device under test (DUT) and a simple stimulus process that assigns all possible signal combinations to the component inputs.

Please create the file tb_and_gate.vhd and enter the following VHDL code:

tb_and_gate.vhd
library IEEE;
use IEEE.std_logic_1164.all;
 
entity TB_AND_GATE is
end TB_AND_GATE;
 
architecture TEST of TB_AND_GATE is
  component AND_GATE
    port (A, B : in std_logic;
             Z : out std_logic);
    end component;
 
  signal W_A, W_B, W_Z : std_logic;
 
begin
  DUT : AND_GATE
    port map(A => W_A,
             B => W_B,
             Z => W_Z);
 
  STIMULI : process
  begin
    W_A <= ’0’;
    W_B <= ’0’;
    wait for 10 ns;
 
    W_A <= ’1’;
    wait for 10 ns;
 
    W_B <= ’1’;
    wait for 10 ns;
 
    W_B <= ’0’;
    wait for 10 ns;
 
    wait;
  end process STIMULI;
end TEST;
 
configuration CFG_TB_AND_GATE of
                   B_AND_GATE is
  for TEST
  end for;
end CFG_TB_AND_GATE;

Prior to simulation you will also have to compile the file, i.e. please run the VHDL analyser (e.g. ’myanalyser and_gate.vhd’; or you have to select a menu entry, e.g. ’analyse’).

Now you are ready to invoke the VHDL simulator if not already done. If not done automatically you have to choose the object to simulate and specify additional simulation parameters. Remember that the configuration is the only VHDL object that can be simulated. Some tools require no (top-) configuration as they built up a default configuration on their own. In this case you can select the top entity for simulation (here it would be TB_AND_GATE). In the other case please select CFG_TB_AND_GATE and press OK to open the simulation control window. The next points describe features which are common to most simulation tools:

Simulation Control

VHDL Synthesis

After you have verified the function of your model with the simulator you can run the synthesis tool. Again you have to analyse the VHDL source code. This is normally done automatically when you read in your VHDL file.

In future tasks/exercises we will define our own packages. The synthesis tool requires that packages are read (analysed) before they are used or referenced. The most frequent errors with the synthesis are missing not read (analysed) packages!