Synthesis
RTL-Style
What is Synthesis
Finite State Machines and VHDL
Introduction
State Processes
State Coding
Medvedev
Moore
Mealy
Registered Output
FSM and Simulation
FSM and Synthesis
Combinational Logic
Combinational Logic
Example of a Multiplier
Differences in Synthesis
Sequential Logic
Advanced Synthesis
Controlling Synthesis
Master-Slave Flip-Flop
Why MSFF?
RS-FF
D-FF
JK-FF
Toggle-FF
Multifunctional-FF
Timing behavior
Quiz