# Examples

```entity PART is
port(terminal inp1, inp2, s, outp: electrical);
end entity PART;

architecture BHV of PART is
constant R: real := 1.0;
constant C : real := 1.5e-9;
terminal int : electrical;
quantity Uint across I through int to ground;
quantity Uinp1 across inp1 to ground;
quantity Uinp1 across inp1 to ground;
quantity Uoutp across outp to ground;
quantity Us across s to ground;
begin
if Us`Above(0.0) use
Uint == Uinp1;
else Uint == Uinp2;
end use;
break on Us`Above(0.0);
I == Uint / R;
Uoutp == -1 / C * I'Integ;
end architecture BHV;```

#### Notes

The interface terminals are declared at the port list, the internal nodes at the architecture declarative part. The operational amplifier is chosen as ideal, that means no potential difference at the input, no input currents an the amplification is infinite. So the potential of the inverting input is ground. All five quantities are declared at the architecture.

The voltage Us controls the switcher. Is it higher than zero volt, Uint is equal to Uinp(1), else Uint is equal to Uinp(2). The change from Uinp(1) to Uinp(2) at Uint is a discontinuity at the following analog part. So, the break signal must be set. The two equations could be combined to one equation, but it is less clear. The number of the unknowns one (the through quantity) like the number of the equations.

```entity PIC is
port(quantity inp  : in real;
quantity outp : out real);
end entity PIC;

architecture SF of PIC is
quantity int : real;
begin
int == inp'Integ;
outp == k1 * inp + k2 * int;
end architecture SF;```

#### Notes

The input and output quantities are declared with the respective mode at the port list. The internal, free quantity int, is no interface, so it is declared at the architecture declarative part.