synthesizeable_vhdl-model-library:patras:functions

Functions

functions.vhd
-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    functions.vhd                                            #
-- #                                                                          #
-- # Library    :    useful_functions                                         #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################
 
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
 
PACKAGE useful_functions IS
 
 FUNCTION log2 (a : INTEGER) RETURN INTEGER;
 FUNCTION vector_eq_zero  (vect : unsigned) RETURN BOOLEAN;
 PROCEDURE Bin2Grey (signal din: in unsigned;
                     signal dout: out unsigned);
 PROCEDURE Grey2Bin (signal din: in unsigned;
                     signal dout: out unsigned);
 
 type stdv_2d is array (natural range <>,natural range <>) of std_ulogic; 
 --  type stdv is array (natural range <>) of unsigned;
 --  type stdv_2d is array (512) of stdv; 
 
END useful_functions;
 
 
PACKAGE BODY useful_functions IS
 
-------------------
-- FUNCTION log2 --
-------------------
 
FUNCTION log2 (a : INTEGER) RETURN INTEGER IS
 VARIABLE result : INTEGER;
 BEGIN
      result := a;
      IF result=1 THEN
      RETURN 1;
      ELSIF result=2 THEN
      RETURN 1;
      ELSIF result=4 THEN
      RETURN 2;
      ELSIF result=8 THEN
      RETURN 3;
      ELSIF result=16 THEN
      RETURN 4;
      ELSIF result=32 THEN
      RETURN 5;
      ELSIF result=64 THEN
      RETURN 6;
      ELSIF result=128 THEN
      RETURN 7;
      END IF; 
 END log2;
 
-----------------------------
-- FUNCTION vector_eq_zero --
-----------------------------
 
FUNCTION vector_eq_zero  (vect : unsigned ) RETURN BOOLEAN IS
VARIABLE len : integer := vect'LENGTH;
VARIABLE vector : unsigned(len-1 downto 0);
VARIABLE equal_zero : BOOLEAN;
BEGIN
-- Check zero equality
equal_zero := true;
for i in len-1 DOWNTO 0 loop
	if vector(i) /= '0' then
		equal_zero := false;
		exit;
	end if;
end loop;
RETURN equal_zero;
END vector_eq_zero;
 
------------------------
-- PROCEDURE Bin2Grey --
------------------------
 
PROCEDURE Bin2Grey (signal din: in unsigned;
		    signal dout: out unsigned) is
-- Both input and output are assumed to be of the same width
BEGIN
dout(din'high) <= din(din'high);
for i in din'low to (din'high - 1) loop
	dout(i) <= din(i+1) xor din(i);
END loop;
END Bin2Grey;
 
------------------------
-- PROCEDURE Grey2Bin --
------------------------
 
PROCEDURE Grey2Bin (signal din: in unsigned;
                    signal dout: out unsigned) is
-- Both input and output are assumed to be of the same width
variable d_int: unsigned (din'range);
BEGIN
d_int(din'high) := din(din'high);
for i in (din'high - 1) downto din'low loop
	d_int(i) := d_int(i+1) xor din(i);
END loop;
dout <= d_int;
END Grey2Bin;
 
END useful_functions;