courses:system_design:project_management:design_components

Design Components

Overview

  • Five basic design units, divided into two groups:
    • Primary units:
      • Entity Entity
      • Package
      • Configuration Configuration
    • Secondary units:
      • Package Body
      • Architecture Architecture
  • Each design unit has to be analysed and stored in a library
  • Packages may be split into header (declarations) and main part

Notes

All parts of a VHDL design have to be analysed/compiled before they can be used for simulation or synthesis.

In total, five different so called design units exist: entity/architecture, package/package body and configuration. A file must contain at least one design unit to be accepted by the compiler.

Libraries

  • Container for compiled design units
    • Entities, architectures,
    • Packages, package bodies,
    • Configurations
  • Mapped to a directory on the filesystem
    • Platform independency
    • Setup file/options setting
  • Different libraries in one design project possible

Desktop Computer

Setup file: 

PROJECT1: /home/user_bill/VHDL_Stuff/project1_lib

Commandline: 

compile -library PROJECT1 p_frame_types.vhd

Notes

After compilation, the design units are stored in a so called “library”.

The purpose of the library mechanism is platform independency, i.e. every VHDL tool has to map the logical library name to a physical directory. If the target library is not specified when compiling a VHDL file, the design units are compiled into the default library ’work’.

It is often mapped to the start-up directory of the software per default.

Special setup files or option settings are needed to specify alternatives. In the example above, the logical library name PROJECT1 is mapped to the physical directory “/home/user_bill/VHDL_Stuff/project1_lib” in the setup files for the simulator and synthesis tool.

This library must be named as target when VHDL files are compiled, i.e. the command will look like “compile -library project1 p_frame_types.vhd”.

Within another VHDL file the library PROJECT1 has to be made visible with the LIBRARY statement if elements of the P_FRAME_TYPES package are to be used.

The LIBRARY Statement

library EXAMPLE;
use EXAMPLE.PKG.all;
 
entity A is
. . .
end A;
 
library EXAMPLE;
use EXAMPLE.PKG.all;
 
entity B is
. . .
end B;
 
architecture BEH of A is
. . .
end BEH;
architecture BEH of B is
. . .
end BEH;
  • Occurrence
    • In front of any design unit (entity, architecture, package, …)
    • Valid for the next unit, only
  • Secondary units “inherit” library declarations
  • Libraries WORK and STD are always known by default
  • Does not declare any VHDL design uni objects
  • Refers to existing libraries
  • Easier design management and preparation
  • May cause visibility problems

Notes

Library statements may only be placed in front of VHDL design units and are valid for the immediately following unit, only.

Secondary design units, however, inherit library declarations that apply to their primary counterparts. Thus, a library clause needs not be repeated in front of an architecture or package body, even when they are placed in separate files (cf. “architecture BEH of B”).

The libraries WORK and STD are visible by default and need not be declared via library statements. Libraries can be used advantageously to separate the object code of different design projects.

The USE Statement

library EXAMPLE;
library OTHER_1;
library OTHER_2;
 
use EXAMPLE.PKG_1.CONST_A,
    EXAMPLE.PKG_1.CONST_B;
 
use EXAMPLE.PKG_2.all;
 
use EXAMPLE.ENTITY_1;
 
architecture BEH of ENTITY_1 is
   use OTHER_1.all;
   signal A : integer;
begin
   A <= OTHER_2.PKG.CONST_A;
end BEH;
  • Occurrence
    • In front of any design unit
    • Valid for the next unit, only
    • May appear in declarative parts, if all items of an object are made visible
  • Secondary units “inherit” use clauses
  • Grants access to individual items
    • Design units (e.g. entities)
    • Objects from packages (e.g. constants)
    • ’all’ accesses all objects
  • Elements of STANDARD package are always accessible by default
  • Complete “logical pathname” needed if ’use’ is omitted

Notes

A library statement alone does not give access to the design units and objects contained in this library.

An additional use clause is necessary for this purpose. Most of the rules concerning its location and consequences are equivalent to the library statement and consequently both statements appear conjunctively most of the time.

A use clause makes individual elements of a library visible within a design unit. It is even possible to select specific objects from a package.

Usually, however, the keyword ’all’ is used to make all its declarations available to the user. The keyword ’all’ is also applicable to complete library contents.

Chapters of System Design > Project Management