courses:system_design:synthesis:finite_state_machines_and_vhdl:pagefooter

Chapters of System Design > Synthesis > Finite State Machines and VHDL

Introduction
State Processes
State Coding
Medvedev
Moore
Mealy
Registered Output
FSM and Simulation
FSM and Synthesis

Chapters of System Design > Synthesis

RTL-Style
What is Synthesis
Finite State Machines and VHDL
Combinational Logic
Sequential Logic
Advanced Synthesis
Controlling Synthesis
Master-Slave Flip-Flop
Quiz