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vhdl_workshop:lab_9 [2017/02/13 16:14] SSE Minion |
vhdl_workshop:lab_9 [2017/02/13 18:06] SSE Minion [Data types] |
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==== Data types ==== | ==== Data types ==== | ||
- | The control signals CLK, REST, TIMER_GO and EXPOSE shall be of type **std_ulogic**, | + | The control signals CLK, RESET, TIMER_GO and EXPOSE shall be of type **std_ulogic**, |
==== To do ==== | ==== To do ==== |