vhdl_workshop:lab_6

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vhdl_workshop:lab_6 [2017/02/13 13:49]
SSE Minion created 		vhdl_workshop:lab_6 [2017/02/15 14:31]
SSE Minion [Synopsis]
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 The complete interface of the register is shown in the following figure: The complete interface of the register is shown in the following figure:
  
-TODO Bild The exposure time latch+{{:vhdl_workshop:workshop_register.svg?nolink&350|The exposure time latch}}
  
 ==== Behaviour ==== ==== Behaviour ====
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 ==== Data types ==== ==== Data types ====
-The exposure latch is used to store the exposure time, i.e. **T_DISPLAY** is the appropriate type for the data signals. CLK and RESET are single bit control signals and shall therefore be of type **std_ulogic**.+The exposure latch is used to store the exposure time, i.e. **T_DIGITS** is the appropriate type for the data signals. CLK and RESET are single bit control signals and shall therefore be of type **std_ulogic**.
  
 ==== To do ==== ==== To do ====
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 end CFG_TB_EXP_FF; end CFG_TB_EXP_FF;
 </code> </code>
 +
 +===== Package =====
 +{{page>.:package}}