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sidebarmenu [2017/11/13 17:51]
Enrico 		sidebarmenu [2017/11/13 17:56]
Enrico
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     * [[:Courses:System Design:VHDL - Overview and Application Field:start|Overview]]     * [[:Courses:System Design:VHDL - Overview and Application Field:start|Overview]]
     * [[:Courses:System Design:VHDL Language and Syntax:start|Syntax]]     * [[:Courses:System Design:VHDL Language and Syntax:start|Syntax]]
-    * [[:Courses:System Design:Synthesis:start]] +    * [[:Courses:System Design:Synthesis:start|Synthesis]] 
-    * [[:Courses:System Design:Simulation:start]] +    * [[:Courses:System Design:Simulation:start|Simulation]] 
-    * [[:Courses:System Design:Project Management:start]] +    * [[:Courses:System Design:Project Management:start|Project Management]] 
-    * [[:Courses:System Design:VHDL vs Verilog:start]]+    * [[:Courses:System Design:VHDL vs Verilog:start|VHDL vs Verilog]]
   * [[:VHDL-AMS:start|VHDL-AMS]]   * [[:VHDL-AMS:start|VHDL-AMS]]
-    * [[:VHDL-AMS:Introduction:start]] +    * [[:VHDL-AMS:Introduction:start|Introduction]] 
-    * [[:VHDL-AMS:New Data Types:start]] +    * [[:VHDL-AMS:New Data Types:start|New Data Types]] 
-    * [[:VHDL-AMS:Examples]] +    * [[:VHDL-AMS:Examples|Examples]] 
-    * [[:VHDL-AMS:Subsumption and Outlook]]+    * [[:VHDL-AMS:Subsumption and Outlook|Subsumption and Outlook]]
   * [[:VHDL Workshop:start|VHDL Workshop]]   * [[:VHDL Workshop:start|VHDL Workshop]]
   * [[:VHDL Reference 93:start|VHDL Reference]]   * [[:VHDL Reference 93:start|VHDL Reference]]