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-  * <text size="medium">[[:Courses:System Design:start|VHDL Tutorial]]</text> +
-    * [[:Courses:System Design:VHDL - Overview and Application Field:start|Overview]] +
-    * [[:Courses:System Design:VHDL Language and Syntax:start|Syntax]] +
-    * [[:Courses:System Design:Synthesis:start]] +
-    * [[:Courses:System Design:Simulation:start]] +
-    * [[:Courses:System Design:Project Management:start]] +
-    * [[:Courses:System Design:VHDL vs Verilog:start]] +
-  * <text size="medium">[[:VHDL-AMS:start|VHDL-AMS]]</text> +
-    * [[:VHDL-AMS:Introduction:start]] +
-    * [[:VHDL-AMS:New Data Types:start]] +
-    * [[:VHDL-AMS:Examples]] +
-    * [[:VHDL-AMS:Subsumption and Outlook]] +
-  * <text size="medium">[[:VHDL Workshop:start|VHDL Workshop]]</text> +
-  * <text size="medium">[[:VHDL Reference 93:start|VHDL Reference]]</text> +
-  * <text size="medium">[[:VHDL Glossary:start|VHDL Glossary]]</text> +
-  * <text size="medium">[[:Synthesizeable VHDL-Model-Library:start|VHDL Library]]</text>+
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