https://www.vhdl-online.de/ 2026-04-29T14:17:13+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2017-02-15T12:14:30+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_1?rev=1487160870&do=diff LAB 1: A Multiplexer Synopsis Your first task is to write the VHDL description of a multiplexer. The camera display shall either show the number of pictures that have already been taken or the current exposure time. The following figure shows a schematic of the multiplexer: text/html 2017-02-15T12:20:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_2?rev=1487161224&do=diff LAB 2: Extending the Multiplexer Synopsis As the module will be used to multiplex single digit values later on, the bus widths need to be adjusted. This is easily done by specifying a range for all data signals which are of type integer. Additionally, error conditions shall also be signaled to the user via the camera display. Therefore, an additional control input named ERROR is needed. The following figure shows the updated schematic: text/html 2017-02-15T13:13:59+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_3?rev=1487164439&do=diff LAB 3: A 7-Segment Display Driver Synopsis As the data has to appear on a 7-segment display it is not sufficient just to multiplex the incoming signals. The information also has to be transformed from a binary representation into a vector of seven driver signals, one per display element. In order to enhance the readability of the VHDL code, constants should be used to represent the various numbers, i.e. text/html 2017-02-14T13:41:23+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_4?rev=1487079683&do=diff LAB 4: A Three Digit 7-Segment Display Driver Synopsis In the final version, DISP_DRV has to drive a 7-segment display with three digits. Other than that, the design needs not to be modified. The most convenient way to handle the data within the design is to define a new type, i.e. an array of three integer respective bit vector values. As user-defined types are already used it is only necessary to change the definition of T_DIGITS respective T_DISPLAY. text/html 2017-02-15T13:24:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_5?rev=1487165046&do=diff LAB 5: A Decoder Synopsis The camera has a different button for each exposure time, i.e. the data signals from the keypad are transferred via a 10-bit data bus. If a button is pressed, the corresponding wire is set to 1. The exposure times are calculated according to the following formula: text/html 2017-02-15T13:31:22+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_6?rev=1487165482&do=diff LAB 6: A Register Synopsis When an exposure time is selected by the user it has to be stored. Edge-triggered Flip-Flops are used for this purpose. The contents of the register are updated only with the rising edge of the clock signal. This way, differences in the path delay become irrelevant as long as the maximum delay is shorter than the clock period. text/html 2017-02-15T15:28:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_7?rev=1487172495&do=diff LAB 7: A State Machine for the Display Synopsis In order to control the 7-segment display a simple state machine is necessary. In addition to the buttons for the desired exposure time another special button is present on the camera panel that allows the user to switch between the current exposure time and the number of pictures that have already been taken. text/html 2017-02-15T15:37:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_8?rev=1487173033&do=diff LAB 8: A Timer Synopsis After a picture has been taken, the film is transported forward automatically. In order to detect malfunction, e.g. end of film or a torn film, a transport supervision module needs to be implemented. If the servo motor has not finished the film transport after 2 seconds, an error signal is generated. text/html 2017-02-15T16:27:34+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_9?rev=1487176054&do=diff LAB 9: A BCD-Counter Synopsis The desired exposure time and the number of pictures are stored in BCD (Binary Coded Decimal) format. This means that every decimal digit is coded by its binary value. Therefore, two times 4 bits are needed to represent the decimal number ’15’. If a binary representation was used, 4 bits would be enough. text/html 2017-02-15T16:42:09+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_10?rev=1487176929&do=diff LAB 10: A State Machine for the Main Controller Synopsis A main control unit is needed to coordinate the actions of the different modules. The interface of the module is depicted in the next drawing: [The main controller interface] When the trigger button is pressed the shutter shall be opened and stay opened for the selected exposure time. This is done by setting the TIMER_GO signal one period to high, so the exposure controller opens the shutter for the selected exposure time. After the ex… text/html 2017-02-15T16:54:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/lab_11?rev=1487177698&do=diff LAB 11: The Camera Synopsis Now all submodules must be merged into one design, the complete camera controller. So all modules have to be connected on a new level of hierarchy. This is called structural modelling. Structural modelling means the use (instantiation) and wiring of components resulting in a net list. VHDL provides the following means for structural modelling: text/html 2017-02-14T13:40:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/package?rev=1487079655&do=diff LAB 4, 5, 6, 7, 8, 9, 10, 11 library ieee; use ieee.std_logic_1164.all; package P_DISPLAY is type T_DIGITS is array (2 downto 0) of integer range 0 to 10; type T_DISPLAY is array (2 downto 0) of std_ulogic_vector(6 downto 0); constant SEG_0 : std_ulogic_vector(6 downto 0):= "0111111"; constant SEG_1 : std_ulogic_vector(6 downto 0):= "0000011"; constant SEG_2 : std_ulogic_vector(6 downto 0):= "1101101"; constant SEG_3 : std_ulogic_vector(6 downto 0):= "1100111"; constant SEG_… text/html 2017-02-13T12:16:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/pagefooter?rev=1486988210&do=diff ---------- * Intro * LAB 1 * LAB 2 * LAB 3 * LAB 4 * LAB 5 * LAB 6 * LAB 7 * LAB 8 * LAB 9 * LAB 10 * LAB 11 text/html 2017-02-15T11:06:21+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_workshop/start?rev=1487156781&do=diff VHDL Workshop: Camera * LAB 1: A Multiplexer * LAB 2: Extending the Multiplexer * LAB 3: A 7-Segment Display Driver * LAB 4: A Three Digit 7-Segment Display Driver * LAB 5: A Decoder * LAB 6: A Register * LAB 7: A State Machine for the Display * LAB 8: A Timer * LAB 9: A BCD-Counter * LAB 10: A State Machine for the Main Controller * LAB 11: The Camera Introduction This VHDL teaching program is divided into several exercises. By writing typical VHDL programs you learn ho…