https://www.vhdl-online.de/ 2026-05-02T08:24:23+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2016-07-21T13:08:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/abstract_literals?rev=1469106519&do=diff Abstract literals Definition abstract_literal * decimal_literal * based_literal decimal_literal integer [ . integer ] [ exponent ] based_literal base # based_integer [ . based_integer ] # [ exponent ] base * integer based_integer extended_digit { [ underline ] extended_digit } text/html 2016-07-01T11:37:23+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/access_types?rev=1467373043&do=diff Access types Definitions access_type_definition access subtype_indication By declaring an access type an access type is declared which can later be used for declaring an index variable. incomplete_type_declaration type identifier By giving an incomplete type declaration it is possible to model recursive structures. The complete type declaration has to be made in the same declarative range. text/html 2016-07-19T08:12:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/adding_operators?rev=1468915944&do=diff Adding operators Definition The addition operators + and - are predefined in their known meaning for every numerical type. The concatenation operator & is predefined for any one-dimensional array type. Overview Operator Operation Operand type (left) text/html 2016-07-05T14:41:44+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/aggregates?rev=1467729704&do=diff Aggregates Definitions aggregate ( element_association { , element_association } ) element_association [ choices => ] expression choices choice { | choice } choice * simple_expression * discrete_range * element _simple_name * others Examples This aggregate has the width 4. (a_bit, b_bit, c_bit, d_bit) text/html 2016-07-18T11:40:30+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/alias_declarations?rev=1468842030&do=diff Alias declarations alias_declaration alias alias_designator [ : subtype_indication ] is name [ signature ] ; Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part text/html 2016-07-05T15:58:51+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/allocator?rev=1467734331&do=diff Allocator Definition allocator * new subtype_indication * new qualified_expression Examples Memory is allocated for the type node . In the first example the default-value of the type node is used for initialization, in the second example the values stated in brackets are used. NEW node NEW node'( 15 ns, NULL ) NEW node'( delay => 5 ns, next => stack ) text/html 2016-07-07T11:29:59+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/architecture?rev=1467890999&do=diff Architecture architecture_body architecture identifier of entity _name is architecture_declarative_part begin architecture_statement_part end [ architecture ] [ architecture _simple_name ] ; Further definitions identifier * text/html 2016-07-19T11:44:52+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/assertion?rev=1468928692&do=diff Assertion assertion_statement [ label : ] assertion ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions assertion assert condition [ report expression ] [ severity expression ] condition text/html 2016-07-18T12:10:41+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/attribute_declarations?rev=1468843841&do=diff Attribute declarations attribute_declaration attribute identifier : type_mark ; Attributes can be used to poll the characteristics of objects (e.g. signals). In many cases this allows a shorter and more elegant VHDL description to be created. The most important attributes are text/html 2016-07-18T15:03:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/attribute_names?rev=1468854235&do=diff Attribute names Definitions attribute_name prefix [ signature ] ' attribute_designator [ ( expression ) ] Examples The left element of the first dimension of the one- or multi-dimensional array register is addressed. register'left(1) ---------- The attribute fanout provides the number of signals driven by text/html 2016-07-18T14:06:26+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/attribute_specification?rev=1468850786&do=diff Attribute specification attribute_specification attribute attribute_designator of entity_specification is expression ; Parents * entity_declarative_part * architecture_declarative_part * configuration_declarative_part * package * block_declarative_part text/html 2016-06-27T08:37:45+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/bit_string_literals?rev=1467016665&do=diff Bit string literals Definition bit_string_literal base_specifier " [ bit_value ] " base_specifier * B * O * X bit_value extended_digit { [ underline ] extended_digit } extended_digit * digit * letter Comments B means binary, O means octal and X means hexadecimal. text/html 2016-07-19T14:48:38+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/block?rev=1468939718&do=diff Block block_statement block _label : block [ ( guard _expression ) ] [ is ] block_header block_declarative_part begin block_statement_part end block [ block _label ] ; Parents * architecture_statement_part Further definitions text/html 2016-10-29T23:29:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/bnf?rev=1477783797&do=diff BNF abstract_literal abstract_literal ::= decimal_literal | based_literal access_type_definition access_type_definition ::= access subtype_indication actual_designator actual_designator ::= expression | signal _name | variable _name | file _name | open text/html 2016-07-19T14:09:48+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/case?rev=1468937388&do=diff CASE case_statement case expression is case_statement_alternative { case_statement_alternative } end case [ case_label ] ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definition text/html 2016-07-21T14:08:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/character_literals?rev=1469110099&do=diff Character literals Definition character_literal ' graphic_character ' Examples 'A' '*' ''' ' ' text/html 2016-06-27T13:00:12+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/character_set?rev=1467032412&do=diff Character set Definitions graphic_character * basic_graphic_character * lower_case_letter * other_special_character basic_character * basic_graphic_character * format_effector basic_graphic_character * upper_case_letter * digit * text/html 2016-06-27T08:32:53+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/comments?rev=1467016373&do=diff Comments Definition Comments are used to explain VHDL-Code. Examples -- last sentence before the ALGOL 68-report is given END ; -- line is no longer worked upon -- an extensive comment can be subdivided into two -- or more successive lines ------- the first two hyphens introduce the comment text/html 2016-07-18T12:13:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/component_declarations?rev=1468844030&do=diff Component declarations component_declaration component identifier [ is ] local _generic_clause ] [ local _port_clause ] end component [ component _simple_name ] ; Parents * architecture_declarative_part * package * block_declarative_part text/html 2016-07-19T15:39:02+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/component_instantiation?rev=1468942742&do=diff Component instantiation component_instantiation_statement instantiation _label : instantiated_unit [ generic_map_aspect ] [ port_map_aspect ] ; Parents * architecture_statement_part * block_statement_part Further definitions text/html 2016-07-01T11:16:10+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/compound_types?rev=1467371770&do=diff Compound types Definitions composite_type_definition * array_type_definition * record_type_definition Examples mt_word is declared as a bit vector of the width 32, with the indices rising from left to right. TYPE my_word IS ARRAY ( 0 TO 31 ) OF bit ; ---------- data_in is declared as a vector of the type text/html 2016-07-19T15:11:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/concurrent_assertion?rev=1468941096&do=diff Concurrent assertion concurrent_assertion_statement [ label : ] [ postponed ] assertion ; Parents * entity_statement_part * architecture_statement_part * block_statement_part Further definitions label * identifier assertion assert condition [ report text/html 2016-07-19T15:06:16+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/concurrent_procedure_call?rev=1468940776&do=diff Concurrent procedure call concurrent_procedure_call [ label : ] [ postponed ] procedure_call ; Parents * entity_statement_part * architecture_statement_part * block_statement_part Further definitions procedure_call procedure _name [ ( actual_parameter_part ) ] Comment text/html 2016-07-19T15:28:50+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/concurrent_signal_assignment?rev=1468942130&do=diff Concurrent signal assignment ,... <= ..." concurrent_signal_assignment_statement [ label : ] [ postponed ] conditional_signal_assignment [ label : ] [ postponed ] selected_signal_assignment Parents * architecture_statement_part * block_statement_part text/html 2016-07-07T11:38:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/configuration?rev=1467891516&do=diff Configuration configuration_declaration configuration identifier of entity _name is configuration_declarative_part block_configuration end [ configuration ] [ configuration _simple_name ] ; Further definitions identifier * basic_identifier * text/html 2016-07-18T14:17:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/configuration_specification?rev=1468851438&do=diff Configuration specification configuration_specification for component_specification binding_indication ; Parents * architecture_declarative_part * block_declarative_part Further definitions component_specification instantiation_list : component _name binding_indication text/html 2016-07-01T10:50:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/conformance_rules?rev=1467370215&do=diff Conformance rules Definition Should the syntax rules require or allow the multiple-specification of a subprogram the following variations are permitted: * One numeric variable can only be replaced by another numeric variable if both variables possess the same value. text/html 2016-07-07T15:00:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/constant_declarations?rev=1467903615&do=diff Constant declarations constant_declaration constant identifier_list : subtype_indication [ := expression ] ; Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part text/html 2016-06-27T13:00:35+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/delimiters?rev=1467032435&do=diff Delimiters Specification (a) delimiter & ' () * + , - . / : ; < = > | (b) compound_delimiter => ** := /= >= <= <> Comments Every lexical element has to fit into one line as the end of the line represents a delimiter. text/html 2016-07-21T11:20:59+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/design_units_and_their_analysis?rev=1469100059&do=diff Design units and their analysis library_clause library logical_name_list ; Further definitions logical_name_list logical_name { , logical_name } Comment The LIBRARY -statement can be placed as a context-statement in front of every library module such as entity, architecture, package, package body and configuration. text/html 2016-07-28T12:26:02+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/deutsch?rev=1469708762&do=diff Design Entities und Configurations Entity Beispiele Beispiel für eine Testbench, die keine Ein- oder Ausgänge besitzt. ENTITY testbench IS END testbench ; ---------- Entity für einen 2-Bit-Volladdierer. * X , Y und Cin sind Eingänge vom Typ Bit. text/html 2016-07-18T14:21:26+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/disconnection_specification?rev=1468851686&do=diff Disconnection specification disconnection_specification disconnect guarded_signal_specification after time _expression ; Parents * entity_declarative_part * architecture_declarative_part * package * block_declarative_part Further definitions text/html 2016-07-26T08:55:42+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/dynamic_elaboration?rev=1469523342&do=diff Dynamic elaboration In order to be able to execute program parts which contain sequential statements it is necessary to elaborate these program parts as well. This is done while the model is executed. Here are some examples in which elaboration is carried out dynamically during simulation: text/html 2016-07-10T15:23:43+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/elaboration_and_simulation?rev=1468164223&do=diff Elaboration and simulation Elaboration is defined for declarations, draft hierarchies and statements (including concurrent statements). A construct can only be activated by elaboration. As long as elaboration is not finished the corresponding construct does not exist! text/html 2016-07-10T17:58:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/elaboration_of_a_blockheader?rev=1468173480&do=diff Elaboration of a blockheader The generic-statement [Elaboration of Generic Statement] Elaboration of the generic-declarations contained in the generic-statement is carried out in the given sequence. During that the generic`s subtypes are formed and a generic constant is provided for each of these subtypes. The individual value is only determined when consecutive generic-map statements are elaborated. If this map statements are missing the system uses the corresponding default value of the in… text/html 2016-07-21T12:38:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/elaboration_of_a_declaration?rev=1469104699&do=diff Elaboration of a declaration Elaborating a declaration corresponds to generating the declared construct. The syntactic rules (above all those concerning the validity range) do not allow a construct to be used before the corresponding declaration has been elaborated. text/html 2016-07-25T22:05:07+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/elaboration_of_a_design_hierarchy?rev=1469484307&do=diff Elaboration of a design hierarchy By elaborating a draft hierarchy a number of processes which are linked by nets are generated which can then be executed to simulate the behaviour of the original draft (model). A draft hierarchy which is defined by an entity is translated by elaborating a block statement which corresponds to the external block which is defined by the entity. It is also possible to determine the draft hierarchy by means of a configuration. When this is done, a block statement … text/html 2016-07-17T22:19:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/elaboration_of_a_statement_part?rev=1468793944&do=diff Elaboration of a statement part The elaboration rules are valid for all statement parts except these of an architecture with the attribute FOREIGN . These are elaborated implementation dependent. Block statements The block`s beginning, its declarative part and its statement part are elaborated successively: text/html 2016-07-07T11:28:10+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/entity?rev=1467890890&do=diff Entity entity_declaration entity identifier is entity_header entity_declarative_part [ begin entity_statement_part ] end [ entity ] [ entity _simple_name ] ; Further definitions identifier * basic_identifier * extended_identifier entity_header [ formal _generic_clause ] [ text/html 2016-07-26T09:45:47+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/execution_of_a_model?rev=1469526347&do=diff Execution of a model A generated model is executed by elaborating the user-specified processes . Within the draft hierarchy the core process * monitors and coordinates during simulation the activities of all processes provided by the user, * has signal values transferred and the values of implicitly defined values, such as text/html 2016-07-19T14:35:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/exit?rev=1468938940&do=diff EXIT exit_statement [ label : ] exit [ loop _label ] [ when condition ] ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions label * identifier condition boolean _expression Examples In both cases the loops are left with the text/html 2016-07-18T15:10:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/expression?rev=1468854657&do=diff Expression Definitions expression Each expression is equal to an equation which forms a rule for the calculation of a value. * relation { and relation } * relation { or relation } * relation { xor relation } * relation [ nand relation ] text/html 2016-07-18T11:04:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/file_declarations?rev=1468839898&do=diff File declarations file_declaration file identifier_list : subtype_indication [ file_open_information ] ; Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part text/html 2016-07-07T14:32:42+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/file_types?rev=1467901962&do=diff File types Definitions file_type_definition file of type_mark Examples Two file types string_file and natural_file are declared. They are to contain elements of the type string and natural . TYPE string_file IS FILE OF string TYPE natural_file IS FILE OF natural text/html 2016-07-05T15:29:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/function_call?rev=1467732576&do=diff Function call Definitions function_call function _name [ ( actual_parameter_part ) ] actual_parameter_part parameter _association_list Examples With this function call exnor_out receives the return value of the function exnor . exnor_out <= exnor(in1, in2); ---------- text/html 2016-07-19T15:50:01+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/generate_statement?rev=1468943401&do=diff Generate statement generate_statement generate _label : generation_scheme generate [ { block_declarative_item } begin ] { concurrent_statement } end generate [ generate _label ] ; Parents * architecture_statement_part * block_statement_part text/html 2016-07-18T12:26:35+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/group_declaration?rev=1468844795&do=diff Group declaration group_declaration group identifier : group_ template _name ( group_constituent_list ) ; Parents * entity_declarative_part * architecture_declarative_part * configuration_declarative_part * package * package_body * block_declarative_part text/html 2016-07-18T12:20:44+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/group_template_declarations?rev=1468844444&do=diff Group template declarations group_template_declaration group identifier is ( entity_class_entry_list ) ; Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part text/html 2016-06-27T12:47:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/identifiers?rev=1467031656&do=diff Identifiers Definition identifier * basic_identifier * extended_identifier basic_identifier letter { [ underline ] letter_or_digit } letter_or_digit * letter * digit letter * upper_case_letter * lower_case_letter extended_identifier text/html 2016-07-19T13:55:48+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/if?rev=1468936548&do=diff IF if_statement [ if _label : ] if condition then sequence_of_statements { elsif condition then sequence_of_statements } [ else sequence_of_statements ] end if [ if _label ] ; Parents * function_statement_part text/html 2016-07-18T15:06:43+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/indexed_names?rev=1468854403&do=diff Indexed names Definition indexed_name prefix ( expression { , expression } ) Examples The 5th element of the array register_array is addressed. register_array(5) ---------- The elements with the indices (1024,7) of the two-dimensional array memory_cell are addressed. text/html 2016-07-18T11:34:22+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/interface_declarations?rev=1468841662&do=diff Interface declarations * Interface declarations define interface objects of a precisely defined type. * Interface objects are interface constants, interface signals, interface variables and interface files. interface_list interface_element { ; interface_element } text/html 2016-07-05T14:29:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/literals?rev=1467728955&do=diff Literals Definitions literal * numeric_literal * enumeration_literal * string_literal * bit_string_literal * null numeric_literal * abstract_literal * physical_literal Examples A literal of the type universal_real (abstract type). 3.14159_26536 ---------- A literal of the type universal_integer (abstract type). 5280 ---------- text/html 2016-07-05T12:00:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/logic_operators?rev=1467720039&do=diff Logic operators Definition The logic operators AND , OR , NAND , NOR , XOR, XNOR and NOT are defined for the predefined data types bit and boolean . They can also be used for one-dimensional array-types ( Array ) whose elements are of the type bit or text/html 2016-07-19T14:12:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/loop?rev=1468937539&do=diff LOOP loop_statement [ loop _label : ] [ iteration_scheme ] loop sequence_of_statements end loop [ loop _label ] ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions label text/html 2016-07-19T09:45:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/miscellaneous_operators?rev=1468921515&do=diff Miscellaneous operators Definition The unary operator ABS is predefined for any numerical type. The exponentiation operator ** is predefined for any integer-and floating-point type. The right operand (= exponent) is always of the predefined type integer text/html 2016-07-05T14:04:34+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/multiplying_operators?rev=1467727474&do=diff Multiplying operators Definition The multiplying operators * and / are predefined in their meaning for every integer- and floating-point type. The operators MOD and REM are predefined for any integer type. The result of every operation is of the same type as the operands (which are also of the same type). text/html 2016-07-18T15:07:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/name?rev=1468854459&do=diff Name Definition name * simple_name * operator_symbol * selected_name * indexed_name * slice_name * attribute_name text/html 2016-07-19T14:25:11+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/next?rev=1468938311&do=diff NEXT next_statement [ label : ] next [ loop _label ] [ when condition ] ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions label * identifier condition boolean _expression Examples In both examples the statements following the text/html 2016-07-19T14:42:30+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/null?rev=1468939350&do=diff NULL null_statement [ label : ] null ; Parents * function_statement_part * procedure_statement_part * process_statement_part Example The NULL -statement explicitly prevents any action from being carried out. NULL ; text/html 2016-07-07T12:30:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/overloading?rev=1467894606&do=diff Overloading Subprogram overloading Subprograms which have the same name but different behaviour are declared as usual. This applies to both procedures and functions. According to the following criteria it has to be possible to choose exactly one procedure or function ( text/html 2016-07-07T13:04:51+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/package_body?rev=1467896691&do=diff Package body package_body package body package _simple_name is package_body_declarative_part end [ package body ] [ package _simple_name ] ; Further definitions simple_name * identifier package_body_declarative_part { package_body_declarative_item } Examples The objects from the library text/html 2016-07-07T12:57:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/package_declaration?rev=1467896235&do=diff Package declaration package_declaration package identifier is package_declarative_part end [ package ] [ package _simple_name ] ; Further definitions identifier * basic_identifier * extended_identifier package_declarative_part { package_declarative_item } simple_name * identifier Examples Declaration of the package text/html 2016-07-07T10:55:00+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/package_standard?rev=1467888900&do=diff Package STANDARD PACKAGE STANDARD IS -- predefined enumeration types: TYPE severity_level IS ( note, warning, error, failure ) ; TYPE boolean IS ( false, true ) ; TYPE bit IS ( '0', '1' ) ; TYPE character IS ( NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL, BS, HT, LF, VT, FF, CR, SO, SI, DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB, CAN, EM, SUB, ESC, FSP, GSP, RSP, USP, ' ', '!', '"', '#', '$', '%', '&', ''', '(', ')', '*', '+', ',', '-', '.', '/', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', ':', '… text/html 2016-06-24T09:35:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/package_textio?rev=1466760904&do=diff Package TEXTIO PACKAGE TEXTIO IS -- type definitions for text I/O : TYPE line IS ACCESS string; TYPE text IS FILE OF string; TYPE side IS ( right, left ); SUBTYPE width IS natural; -- standard text files : -- old VHDL'87 standard -- FILE input : text IS IN "std_input"; -- FILE output : text IS OUT "std_output"; -- new VHDL'93 standard FILE input : text OPEN READ_MODE IS "std_input"; FILE output : text OPEN WRITE_MODE IS "std_output"; -- input routines for stand… text/html 2016-06-27T08:10:23+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/predefined_attributes?rev=1467015023&do=diff Predefined attributes T'BASE Kind type Prefix any type or subtype T Result type base type of T Restrictions This attribute can only be used as a prefix for the names of other attributes, e.g., T'BASE'LEFT. T'LEFT Kind value Prefix any scalar type or subtype T text/html 2016-07-19T13:50:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/procedure_call?rev=1468936218&do=diff Procedure call procedure_call_statement [ label : ] procedure_call ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions label * identifier procedure_call procedure _name [ ( actual_parameter_part ) ] Examples The procedure text/html 2016-07-19T14:54:48+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/process?rev=1468940088&do=diff Process process_statement [ process _label : ] [ postponed ] process [ ( sensitivity_list ) ] [ is ] process_declarative_part begin process_statement_part end [ postponed ] process [ process _label ] ; Parents * entity_statement_part text/html 2016-07-05T15:47:49+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/qualified_expression?rev=1467733669&do=diff Qualified Expression Definitions qualified_expression * type_mark ' ( expression ) * type_mark ' aggregate Examples The type of the individual return value is explicitly selected by the qualified expressions. Thus, the corresponding `=`-function is selected as well. w <= (a=b) = (c=d); x <= (a=b) = mvl4'(c=d); y <= (a=b) = bit'(c=d); z <= (a=b) = boolean'(c=d); text/html 2016-07-18T14:58:21+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/range_names?rev=1468853901&do=diff Range names Definition slice_name prefix ( discrete_range ) Example Different slices are addressed. * The first slice addresses the range 0 to 7 of r15 . * The second slice addresses the range 24 to 1 of data . * The third slice is invalid as the direction of indication in the declaration is opposed to that in the slice. text/html 2016-07-05T12:52:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/relational_operators?rev=1467723144&do=diff Relational operators Definition * Comparing operators are used to compare operands according to their equality, inequality and size. * The operands always have to be of the same type. * The result of the operation is of the predefined type boolean text/html 2016-06-27T08:28:29+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/replacing_characters?rev=1467016109&do=diff Replacing characters Definition A vertical line (|) can be replaced by an exclamation mark (!), which represents an operation character ( delimiter ). The number signs (#) in based literals can be replaced by colons (:) if both characters are replaced. text/html 2016-07-19T11:56:34+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/report?rev=1468929394&do=diff Report report_statement [ label : ] report expression [ severity expression ] ; Parents * function_statement_part * procedure_statement_part * process_statement_part Comments The REPORT expression have to be of type string. text/html 2016-06-27T08:30:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/reserved_words?rev=1467016258&do=diff Reserved words Specification ABS ACCESS AFTER ALIAS ALL AND ARCHITECTURE ARRAY ASSERT ATTRIBUTE BEGIN BLOCK BODY BUFFER BUS CASE COMPONENT CONFIGURATION CONSTANT DISCONNECT DOWNTO ELSE ELSIF END ENTITY EXIT FILE FOR FUNCTION GENERATE GENERIC GROUP GUARDED IF IMPURE IN INERTIAL INOUT IS LABEL LIBRARY LINKAGE LITERAL LOOP MAP MOD NAND NEW NEXT NOR NOT NULL OF ON OPEN OR OTHERS OUT PACKAGE PORT POSTPONED PROCEDURE PROCESS PURE RANGE RECORD REGISTER REM REPORT ROL ROR RETURN SELECT … text/html 2016-07-07T12:45:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/resolution_function?rev=1467895536&do=diff Resolution function Definition A resolution function determines a signal`s value if this signal receives assignments from more than one source at a time. This is necessary if the following concurrent assignments to the unresolved signal Z exist. Examples: text/html 2016-07-19T14:38:29+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/return?rev=1468939109&do=diff RETURN return_statement [ label ] return [ expression ] ; Parents * function_statement_part * procedure_statement_part Further definitions label * identifier expression * relation { and relation } * relation { or relation } * relation { xor relation } text/html 2016-07-07T14:15:23+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/scalar_types?rev=1467900923&do=diff Scalar types Definitions scalar_type_definition * enumeration_type_definition * integer_type_definition * floating_type_definition * physical_type_definition Examples Different types are declared. * Types Bit and switch_level are declared as enumeration types through characters and can only have the values ' 0' or ' 1' and 'X '. One has to distinguish between these values ' text/html 2016-07-05T11:01:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/selected_names?rev=1467716500&do=diff Selected names Definitions selected_name prefix . suffix prefix * name * function_call suffix * simple_name * character_literal * operator_symbol * all Examples The element opcode of the Record instruction is addressed. instruction.opcode ---------- All elements ( ALL ) to which the index text/html 2016-07-05T13:35:30+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/shift_operators?rev=1467725730&do=diff Shift Operators Definition The Shift Operators are defined for any one-dimensional arrays with elements of type BIT or BOOLEAN . The operators are defined as follows, where L is the left operand and R the right operand: * L sll R : Shift L logically left (R≥0) respective right (R<0) by R index positions. The foremost (R≥0) respective the last (R<0) elements drop out and T'LEFT is inserted. T is the type of the elements of the array. text/html 2016-07-19T12:11:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/signal_assignment?rev=1468930317&do=diff Signal assignment ... <= ..." signal_assignment_statement [ label : ] target <= [ delay_mechanism ] waveform ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions delay_mechanism transport text/html 2016-07-18T09:10:18+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/signal_declarations?rev=1468833018&do=diff Signal declarations signal_declaration signal identifier_list : subtype_indication [ signal_kind ] [ := expression ] ; Parents * entity_declarative_part * architecture_declarative_part * package * block_declarative_part * procedure_declarative_part text/html 2016-07-18T15:07:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/simple_names?rev=1468854435&do=diff Simple names Definition simple_name * identifier With a simple name different objects in VHDL-Code can be addressed and manipulated. text/html 2016-06-22T15:08:14+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/start?rev=1466608094&do=diff VHDL Reference '93 * Design entities and configurations * Entity * Architecture * Configuration * Subprograms and packages * Subprogram declaration * Subprogram body * Overloading * Resolution function * Package declaration * Package body * Conformance rules * Types * Scalar types * Compound types * Access types * File types * Declarations * Type declarations * Subtype declarations * Constant declarations * Signal declarations *… text/html 2016-07-06T08:11:05+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/static_expression?rev=1467792665&do=diff Static expression Definition There are two categories of static expressions. An expression is called locally static if every operator in the expression is an implicit defined operator, if both operands and results are scalar and every primary in the expression is a text/html 2016-07-21T14:12:07+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/string_literals?rev=1469110327&do=diff String literals Definition string_literal " { graphic_character } " Comments * A character string must not extend to the following lines as it is a lexical element. * Character strings which do not fit into one line can be divided into two or more character strings and be chained or linked to each other. (see the example). text/html 2016-07-07T12:02:58+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/subprogram_body?rev=1467892978&do=diff Subprogram body subprogram_body subprogram_specification is subprogram_declarative_part begin subprogram_statement_part end [ subprogram_kind ] [ designator ] ; Parent * entity_declarative_part * architecture_declarative_part * package text/html 2016-07-07T11:54:09+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/subprogram_declaration?rev=1467892449&do=diff Subprogram declaration subprogram_declaration subprogram_specification ; Parent * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part * procedure_declarative_part text/html 2016-07-07T14:57:40+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/subtype_declarations?rev=1467903460&do=diff Subtype declarations subtype_declaration subtype identifier is subtype_indication ; Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part * procedure_declarative_part text/html 2016-07-19T10:13:38+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/type_conversion?rev=1468923218&do=diff Type conversion Definitions type_conversion type_mark ( expression ) Examples The float_variable is turned into an integer type by rounding up/down. integer(float_varibale) ---------- The integer_variable is turned into the type real. real(integer_variable) text/html 2016-07-07T14:38:32+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/type_declarations?rev=1467902312&do=diff Type declarations type_declaration * full_type_declaration * incomplete_type_declaration Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part * function_declarative_part text/html 2016-07-06T08:15:04+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/universal_expression?rev=1467792904&do=diff Universal expression Definition A universal expression is an expression whose results are either of the type universal integer or universal real . Overview Operator Operation Operand type (left) Operand type (right) Result type * Multiplication text/html 2016-07-21T11:18:38+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/use-statements?rev=1469099918&do=diff Use-statements use_clause use selected_name { , selected_name } ; Parents * entity_declarative_part * architecture_declarative_part * configuration_declarative_part * package * package_body * block_declarative_part * function_declarative_item text/html 2016-07-19T13:02:47+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/variable_assignment?rev=1468933367&do=diff Variable assignment ... := ..." variable_assignment_statement [ label : ] target := expression ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions label * identifier target * name * aggregate expression text/html 2016-07-18T09:33:17+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/variable_declarations?rev=1468834397&do=diff Variable declarations variable_declaration [ shared ] variable identifier_list : subtype_indication [ := expression ] ; Parents * entity_declarative_part * architecture_declarative_part * package * package_body * block_declarative_part text/html 2016-07-21T10:54:46+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/visibility_and_validity_ranges?rev=1469098486&do=diff Visibility and validity ranges Declarative range Declarative ranges are parts of the description text. Separate, declarative ranges are: * Entity-declarations together with their corresponding architecture bodies * Configuration declarations * text/html 2016-07-19T11:30:03+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/vhdl_reference_93/wait?rev=1468927803&do=diff Wait wait_statement [ label : ] wait [ sensitivity_clause ] [ condition_clause ] [ timeout_clause ] ; Parents * function_statement_part * procedure_statement_part * process_statement_part Further definitions label * identifier sensitivity_clause