VHDL-Online - courses:system_design:vhdl_language_and_syntax:vhdl_structural_elements

component

Anonymous (anonymous@undisclosed.example.com) — 2015-12-09T15:32:34+00:00

Component Hierarchical Model Layout [Full Adder] Full adder: 2 halfadders + 1 OR-gate Notes VHDL allows for a hierarchical model layout, which means that a module can be assembled out of several submodules. The connections between these submodules are defined within the architecture of a top module. As you can see, a fulladder can be built with the help of two halfadders (module1, module2) and an OR gate (module3).

configuration

Anonymous (anonymous@undisclosed.example.com) — 2015-12-09T15:39:15+00:00

Configuration Configuration: Introduction [Configuration] entity HALFADDER is port(A, B : in bit; SUM, CARRY : out bit); end HALFADDER; ... component HALFADDER port(A, B : in bit; SUM, CARRY : out bit); end HALFADDER; signal W_SUM : bit; signal W_CARRY1, W_CARRY2: bit; ... MODULE1: HALFADDER port map(A, B, W_SUM, W_CARRY1);

entity_and_architecture

Anonymous (anonymous@undisclosed.example.com) — 2016-05-26T12:53:34+00:00

Entity and Architecture Entity [Entity] entity HALFADDER is port(A, B : in bit; SUM, CARRY : out bit); end HALFADDER; -- VHDL’93: end entity HALFADDER; entity ADDER is port(A, B: in integer range 0 to 3; SUM : out integer range 0 to 3; CARRY: out bit); end ADDER;

outlook_and_summary

Anonymous (anonymous@undisclosed.example.com) — 2015-12-09T16:21:17+00:00

Outlook and Summary Outlook: Testbench [Testbench] * VHDL code for top level * No interface signals * Instantiation of design * Statement for stimuli generation * Simple testbenches: response analysis by waveform inspection * Sophisticated testbenches may need >50% of complete project resources

package_and_library

Anonymous (anonymous@undisclosed.example.com) — 2015-12-11T17:16:05+00:00

Package and Library Package package PROJECT_PACK is -- constants -- data types -- components -- sub routines end PROJECT_PACK; [Package] * Collection of definitions, data types, subprograms * Reference made by the design team

pagefooter

Anonymous (anonymous@undisclosed.example.com) — 2015-11-12T19:11:47+00:00

---------- Chapters of System Design > VHDL Language and Syntax > VHDL Structural Elements * VHDL Structural Elements * Entity and Architecture * Component * Configuration * Process * Package and Library * Outlook and Summary * Quiz ---------- Chapters of System Design > VHDL Language and Syntax * General Issues * VHDL Structural Elements * Data Types * Process Execution * Extended Data Types * Operators * Sequential Statements * Subprograms * Subprogram De…

process

Anonymous (anonymous@undisclosed.example.com) — 2015-12-09T15:45:05+00:00

Process Introduction entity AND_OR_XOR is port(A, B : in bit; Z_OR, Z_AND : out bit; Z_XOR : out bit); end AND_OR_XOR; architecture RTL of AND_OR_XOR is begin A_O_X: process (A,B) -- sensitivity list begin Z_OR <= A or B; Z_AND <= A and B; Z_XOR <= A xor B; end process A_O_X; end RTL;

quiz

Anonymous (anonymous@undisclosed.example.com) — 2016-05-26T15:37:00+00:00

Quiz

start

Anonymous (anonymous@undisclosed.example.com) — 2015-12-09T15:10:20+00:00

VHDL Structural Elements VHDL Units Entity: Interface Architecture: Implementation, behavior, function Configuration: Model chaining, structure, hierarchy Process: Concurrency, event controlled Package: Modular design, standard solution, data types, constants