https://www.vhdl-online.de/ 2026-04-29T07:56:06+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2015-12-10T14:16:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/case_statement?rev=1449756979&do=diff CASE Statement Fundamentals case EXPRESSION is when VALUE_1 => -- sequential statements when VALUE_2 | VALUE_3 => -- sequential statements when VALUE_4 to VALUE_N => -- sequential statements when others => -- sequential statements end case; text/html 2015-12-11T16:56:10+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/for_loops?rev=1449852970&do=diff FOR Loops Fundamentals entity FOR_LOOP is   port(A : in integer range 0 to 3;        Z : out bit_vector (3 downto 0)); end FOR_LOOP; architecture EXAMPLE of FOR_LOOP is begin   process (A)   begin     Z <= "0000";     for i in 0 to 3 loop       if (A = i) then         Z(i) <= ‘1’;        end if;     end loop;   end process; end EXAMPLE; text/html 2015-12-10T14:09:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/if_statement?rev=1449756553&do=diff IF Statement Fundamentals if CONDITION then -- sequential statements end if; if CONDITION then -- sequential statements else -- sequential statements end if; if CONDITION then -- sequential statements elsif CONDITION then -- sequential statements ... else -- sequential statements end if; text/html 2015-11-12T19:10:29+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/pagefooter?rev=1447355429&do=diff ---------- Chapters of System Design > VHDL Language and Syntax > Sequential Statements * Sequential Statements * IF Statement * CASE Statement * FOR Loops * WAIT Statement * Variables * Quiz ---------- Chapters of System Design > VHDL Language and Syntax * General Issues * VHDL Structural Elements * Data Types * Process Execution * Extended Data Types * Operators * Sequential Statements * Subprograms * Subprogram Declaration and Overloading * Concurrent St… text/html 2016-04-22T21:51:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/quiz?rev=1461361916&do=diff Quiz text/html 2015-12-10T14:04:27+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/start?rev=1449756267&do=diff Sequential Statements Introduction [Sequential Statements] * Executed according to the order in which they appear * Permitted only within processes and subprograms * Used to describe algorithms Notes All statements in processes or subprograms are processed sequentially, i.e. one after another. text/html 2015-12-10T16:18:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/variables?rev=1449764335&do=diff Variables Fundamentals architecture RTL of XYZ is   signal A, B, C : integer range 0 to 7; signal Y, Z : integer range 0 to 15; begin process (A, B, C) variable M, N : integer range 0 to 7; begin M := A; N := B; Z <= M + N; M := C; Y <= M + N; end process; end RTL; text/html 2015-12-10T16:07:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/vhdl_language_and_syntax/sequential_statements/wait_statement?rev=1449763656&do=diff WAIT Statement Fundamentals * ‘wait’ statement stop the process execution * The Process os continued when the instruction is fulfilled * Different types of wait statement: * wait for a specific time wait for SPECIFIC_TIME; * wait for a signal event