VHDL-Online - courses:system_design:vhdl_language_and_syntax

concurrent_statements

Anonymous (anonymous@undisclosed.example.com) — 2016-04-22T21:59:29+00:00

Concurrent Statements Introduction * Concurrent statements are executed at the same time; * independent of the order in which they appear [Concurrent Statements] Notes All statements within architectures are executed concurrently. While it is possible to use VHDL processes as the only concurrent statement, the necessary overhead (process, begin, end, sensitivity list) lets designer look for alternatives when the sequential behavior of processes is not needed.

data_types

Anonymous (anonymous@undisclosed.example.com) — 2016-06-17T13:00:03+00:00

Data Types Fundamentals entity FULLADDER is port(A, B, CARRY_IN : in bit; SUM, CARRY : out bit); end FULLADDER; architecture MIX of FULLADDER is component HALFADDER port(A, B : in bit; SUM, CARRY : out bit); signal W_SUM, W_CARRY1, W_CARRY2 : bit; begin HA1: HALFADDER port map(A, B, W_SUM, W_CARRY1); HA2: HALFADDER port map(CARRY_IN, W_SUM, SUM, W_CARRY2); CARRY <= W_CARRY1 or W_CARRY2; end MIX;

general_issues

Anonymous (anonymous@undisclosed.example.com) — 2015-12-09T14:18:00+00:00

General Issues Basic Syntax Rules ------------------------------- --Example VHDL Code-- ------------------------------- SIGNAL mySignal : bit; -- an example signal MYsignal <= '0', -- start with '0', '1' AFTER 10 ns, -- and toggle after '0' AFTER 10 ns, -- every 10 ns '1' AFTER 10 ns;

notizen

Anonymous (anonymous@undisclosed.example.com) — 2016-06-20T16:25:52+00:00

Deutsche Notizen General Issues Basic Syntax Rules VHDL ist allgemein unabhängig von Klein- oder Grossschreibung. Dies kann man ausnützen, in dem man hauseigene Formatierungsrichtlinien festlegt. Z.B. könnte man alle VHDL Schlüssewörter klein schreiben und alle selbstgewählten Bezeichner groß, wie dies auch im folgenden der Fall sein wird.

operators

Anonymous (anonymous@undisclosed.example.com) — 2016-12-01T12:17:44+00:00

Operators Overview logical and or nand nor xor xnor not relational = /= < <= >= > shift sll srl sla sra rol ror arithmetic + - * / mod rem ** abs sorted on order of increasing precedence (top ⇒ down)

pagefooter

Anonymous (anonymous@undisclosed.example.com) — 2015-11-12T19:05:14+00:00

---------- Chapters of System Design > VHDL Language and Syntax * General Issues * VHDL Structural Elements * Data Types * Process Execution * Extended Data Types * Operators * Sequential Statements * Subprograms * Subprogram Declaration and Overloading * Concurrent Statements

process_execution

Anonymous (anonymous@undisclosed.example.com) — 2016-04-22T08:19:53+00:00

Process Execution Fundamentals architecture A of E is begin P1 : process begin -- sequential statements end process P1; -- C2: concurrent statements P2 : process begin -- sequential statements end process P2; -- C1: concurrent statements end A;

start

Anonymous (anonymous@undisclosed.example.com) — 2015-11-04T22:38:03+00:00

VHDL Language and Syntax * General Issues * VHDL Structural Elements * VHDL Structural Elements * Entity and Architecture * Component * Configuration * Process * Package and Library * Outlook and Summary * Quiz * Data Types * Process Execution * Extended Data Types * Introduction * Standard Logic Type * Enumeration Types * Arrays * More * Quiz * Operators * Sequential Statements * Sequential Statements * IF Statement * CASE Stat…

subprograms

Anonymous (anonymous@undisclosed.example.com) — 2015-12-10T17:06:25+00:00

Subprograms Introduction * Functions * Function name can be an operator * Arbitrary number of input parameters * Exactly one return value * No WAIT statement allowed * Function call ⇔ VHDL expression * Procedures * Arbitrary number of parameters of any possible direction (in/out/inout)

subprogram_declaration_and_overloading

Anonymous (anonymous@undisclosed.example.com) — 2016-06-20T12:47:07+00:00

Subprogram Declaration and Overloading Introduction * Subprograms may be declared/defined in any declaration part * Package * Entity * Architecture * Process * Subprogram * Overloading of subprograms possible * Identical name