https://www.vhdl-online.de/ 2026-05-01T06:38:31+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2015-12-11T13:55:53+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/d-ff?rev=1449842153&do=diff D-FF Overview [D-FF Circuit] D C Q(t+1) 1 ↑ 1 0 ↑ 0 ↑ = rising edge of clock * transmission-gates = simple switch: [Transmission Gate] * 2 complementary D-Latches are state controlled by clock [D-FF Block] * C=0: master is transparent, following the input level, slave is locked (holds) text/html 2015-12-13T00:16:09+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/jk-ff?rev=1449965769&do=diff JK-FF Overview [JK-FF Circuit] * Q(t+1)=[(Q' and J) or (Q and K')](t) J K C Q(t+1) state 0 0 ↑ Q(t) hold 0 1 ↑ 0 reset 1 0 ↑ 1 set 1 1 ↑ Q(t)' invert ↑ = rising edge of clock * J=K=1 may be used for: inverting (frequency divider, counter) text/html 2015-12-22T20:21:28+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/multifunctional-ff?rev=1450815688&do=diff Multifunctional-FF Overview * Multifunctional-FF * several inputs * Reset, Set, Enable, D1, D2 and so on. * basic block of an ASIC library [Multifunctional-FF] text/html 2015-11-12T13:21:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/pagefooter?rev=1447334479&do=diff ---------- Chapters of System Design > Synthesis > Master-Slave Flip-Flop * Why MSFF? * RS-FF * D-FF * JK-FF * Toggle-FF * Multifunctional-FF * Timing behavior ---------- Chapters of System Design > Synthesis * RTL-Style * What is Synthesis * Finite State Machines and VHDL * Combinational Logic * Sequential Logic * Advanced Synthesis * Controlling Synthesis * Master-Slave Flip-Flop * Quiz text/html 2015-12-12T22:14:51+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/rs-ff?rev=1449958491&do=diff RS flip-flop Introduction [RS-Flipflop Circuit] S R C Q(t+1) state 0 0 ⎍ Q(t) hold 0 1 ⎍ 0 reset 1 0 ⎍ 1 set 1 1 ⎍ - undefined ⎍ = while clock is HIGH * 2 statically clocked RS-Latches (clocked, state-driven) text/html 2015-12-11T23:54:01+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/start?rev=1449878041&do=diff Why MSFF? [Integrated Circuit] integrated circuit = combinational logic + storage elements Master-Slave flip-flop * Binary storage element: stores values 0 or 1 * MS-FF: complete isolation/de-coupling of inputs and outputs * input value is buffered and transfered to the output text/html 2015-12-22T21:46:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/timing_behavior?rev=1450820791&do=diff Timing behavior Fundamentals important for the ASIC Synthesis: * Input-Setup-Time TSU * Input-Hold-Time TH * Output-Delay-Time TOD * Wire-Delay-Time (spez. Clock Skew) Setup/Hold-Time [Voltages] [Voltage Points] [Setup/Hold-Time] D stable while * TSU before the clock edge and text/html 2015-12-22T16:38:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/master-slave_flip-flop/toggle-ff?rev=1450802335&do=diff Toggle-FF Overview T=J=K [Toggle-FF Block] T C Q(t+1) state 1 ↑ Q'(t) invert 0 ↑ Q(t) hold ↑ = rising edge of clock * Q(t+1)=[(Q' and T) or (Q and T')](t) = Q(t) xor T(t) Asynchronous 4 bit binary counter [Asynchronous 4 bit binary counter block diagram] [Asynchronous 4 bit binary counter timing behaviour] simple structure - but problems by application because of real runtimes!!!!