VHDL-Online - courses:system_design:synthesis:finite_state_machines_and_vhdl

fsm_and_simulation

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T15:12:38+00:00

FSM and Simulation Fundamentals * Simulation cycle consists of two phases * Signal update phase * Process execution phase [Simulytion Cycle] * Combinational processes: * Signal update at any time * Process execution with new values and signal updates until no process execution necessary anymore

fsm_and_synthesis

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T15:25:39+00:00

FSM and Synthesis Fundamentals * Many constraints imaginable for synthesis * Mostly used constraints: * Speed → clock period * Area → maximum area set to 0 * Power → maximum power allowed * Operating environments * Port attributes

mealy

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T09:05:55+00:00

FSM: Mealy Fundamentals [Mealy Block Diagram] * The output vector is a function of the state vector and the input vector: Y = f(X,S) Three Processes architecture RTL of MEALY is ... begin REG: -- Clocked Process CMB: -- Combinational Process with Next State Logic OUTPUT: process (STATE, X) begin -- Output Logic end process OUTPUT; end RTL;

medvedev

Anonymous (anonymous@undisclosed.example.com) — 2015-12-11T12:43:31+00:00

FSM: Medvedev Fundamentals [Medvedev State Circuit] * The output vector resembles the state vector: Y = S Two Processes architecture RTL of MEDVEDEV is ... begin REG: process (CLK, RESET) begin -- State Registers Inference end process REG; CMB: process (X, STATE) begin -- Next State Logic end process CMB; Y <= S; -- no output logic end RTL

moore

Anonymous (anonymous@undisclosed.example.com) — 2017-01-23T15:41:20+00:00

FSM: Moore Fundamentals [Moore State Circuit] * The output vector is a function of the state vector: Y = f(S) Three Processes architecture RTL of MOORE is ... begin REG: -- Clocked Process CMB: -- Combinational Process with Next State Logic OUTPUT: process (STATE) begin -- Output Logic end process OUTPUT; end RTL ;

pagefooter

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T12:49:34+00:00

---------- Chapters of System Design > Synthesis > Finite State Machines and VHDL * Introduction * State Processes * State Coding * Medvedev * Moore * Mealy * Registered Output * FSM and Simulation * FSM and Synthesis ---------- Chapters of System Design > Synthesis * RTL-Style * What is Synthesis * Finite State Machines and VHDL * Combinational Logic * Sequential Logic * Advanced Synthesis * Controlling Synthesis * Master-Slave Flip-Flop * Quiz

registered_output

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T10:27:43+00:00

Registered Output Modelling Aspects * Medvedev is too inflexible * Moore is preferred because of safe operation * Mealy more flexible, but danger of * Spikes * Unnecessary long paths (maximum clock period) * Combinational feed back loops

start

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T12:48:23+00:00

Finite State Machines and VHDL Introduction * State Processes * State Coding * FSM (Finite State Machine) Types * Medvedev * The output vector (Y) resembles the state vector (S): Y = S * Moore * The output vector (Y) is a function of the state vector (S): Y = f(S) *

state_coding

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T12:33:35+00:00

State Coding State Encoding * State encoding responsible for safety of FSM type STATE_TYPE is (START, MIDDLE, STOP); signal STATE : STATE_TYPE ; * Default encoding: binary (may vary with synthesis tools and number of states) START -> "00" MIDDLE -> "01" STOP -> "10"

state_processes

Anonymous (anonymous@undisclosed.example.com) — 2017-01-24T12:24:11+00:00

State Processes One "State" Process [State Circuit] FSM_FF: process (CLK, RESET) begin if RESET = ’1’ then STATE <= START; elsif CLK’event and CLK = ’1’ then case STATE is when START => if X = GO_MID then STATE <= MIDDLE; end if; when MIDDLE => if X = GO_STOP then STATE <= STOP; end if; when STOP => if X = GO_START then STATE <= START; end if…