VHDL-Online - courses:system_design:synthesis:combinational_logic

differences_in_synthesis

Anonymous (anonymous@undisclosed.example.com) — 2015-12-11T11:11:43+00:00

Differences in Synthesis Synthesis of Operators * Operator structure * Discrete gates * Macro cell from the library * Operator architecture (e.g. ripple-carry, carry-look-ahead etc.) * Specific comments for the synthesis tool contained in the VHDL code

example_of_a_multiplier

Anonymous (anonymous@undisclosed.example.com) — 2015-12-11T11:06:37+00:00

Example of a Multiplier Introduction [Multiplier Block Diagram] * 2 x 2 bit multiplier * Inputs: A1, A0, B1, B0 : 2 bit * Outputs: C3, C2, C1, C0 : 4 bit entity MULTIPLIER is port (A0 : in bit; A1 : in bit; B0 : in bit; B1 : in bit; C0 : out bit; C1 : out bit; C2 : out bit; C3 : out bit); end MULTIPLIER;

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Anonymous (anonymous@undisclosed.example.com) — 2015-11-12T13:17:53+00:00

---------- Chapters of System Design > Synthesis > Combinational Logic * Combinational Logic * Example of a Multiplier * Differences in Synthesis ---------- Chapters of System Design > Synthesis * RTL-Style * What is Synthesis * Finite State Machines and VHDL * Combinational Logic * Sequential Logic * Advanced Synthesis * Controlling Synthesis * Master-Slave Flip-Flop * Quiz

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Anonymous (anonymous@undisclosed.example.com) — 2015-12-11T10:36:21+00:00

Combinational Logic Feedback Loops architecture EXAMPLE of FEEDBACK is signal B, X : integer range 0 to 99; begin process (X, B) begin X <= X + B; end process; ... end EXAMPLE; [Feedback Loops] Notes When modelling purely combinational logic, it is necessary to avoid combinational feedback loops. A feedback loop triggers itself all the time, i.e. the corresponding process is always active. In the example, this results in a perpetual addition, i.e. X is increased to its…