https://www.vhdl-online.de/ 2026-04-30T16:40:03+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2015-12-11T13:29:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/advanced_synthesis?rev=1449840546&do=diff Advanced Synthesis Parametrization [Constant and Generic] * Constant C identical in all referencing units * Generic G different but constant within each entity * Input signal S set/changed in operation (different operation modes) Notes Once you have finished a design, you hope that you will be able to use at least parts of the VHDL code in other designs as well. (Re-Use) text/html 2015-12-11T23:53:15+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/controlling_synthesis?rev=1449877995&do=diff Controlling Synthesis Synthesis Attributes (IEEE 1076.6 - 2004) * Synthesis tools: can be told to optimize either speed or area * Sometimes finer control is needed ➔ include “attribute specifications” * However, different tools support different attributes text/html 2016-07-25T22:23:33+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/lost_chapters?rev=1469485413&do=diff RTL-Style after “Process Types”: Combinatorics Library IEEE; use IEEE.Std_Logic_1164.all; entity IF_EXAMPLE is port (A, B, C, X : in std_ulogic_vector(3 downto 0); Z : out std_ulogic_vector(3 downto 0)); end IF_EXAMPLE; architecture A of IF_EXAMPLE is begin process (A, B, C, X) begin if ( X = "1110" ) then Z <= A; elsif (X = "0101") then Z <= B; else Z <= C; end if; end process; e… text/html 2016-06-22T11:23:24+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/notizen?rev=1466594604&do=diff Deutsche Notizen RTL-Style Process Types RTL - Register-Transfer-Level. Im Unterschied zur Modellierung auf Verhaltensebene, wo VHDL wie jede andere Programmiersprache verwendet werden kann, liegt die RT-Ebene eine Stufe näher and er Hardware. Dabei wird der Algorithmus aufgeteilt in rein kombinatorische Blöcke und in getaktete Blöcke mit speicherndem Charakter d.h. mit Flip-Flops. Im rein kombinatorischen Block soll kein speicherndes Element beinhaltet sein. Dafür müssen IF-Anweisungen volls… text/html 2016-04-22T10:26:57+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/pagefooter?rev=1461320817&do=diff ---------- Chapters of System Design > Synthesis * RTL-Style * What is Synthesis * Finite State Machines and VHDL * Combinational Logic * Sequential Logic * Advanced Synthesis * Controlling Synthesis * Master-Slave Flip-Flop * Quiz text/html 2016-04-25T11:23:55+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/quiz?rev=1461583435&do=diff Quiz text/html 2016-04-22T21:56:39+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/rtl-style?rev=1461362199&do=diff RTL-Style Process Types [RTL-Style] Notes In RTL (Register Transfer Level) style modelling, the design is split up into storing elements, i.e. flip flops or often simply called registers, and combinational logic which constitute the transfer function from one register to the succeeding register. text/html 2016-04-25T11:22:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/sequential_logic?rev=1461583356&do=diff Sequential Logic Sequential logic is the general term for designs containing storing elements, especially flip flops. Initialization * A reset mechanism is required in hardware to initialize all registers * Asynchronous reset behavior can be modelled with processes with sensitivity list, only text/html 2017-01-24T12:50:19+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/start?rev=1485262219&do=diff Synthesis * RTL-Style * What is Synthesis * Finite State Machines and VHDL * Introduction * State Processes * State Coding * Medvedev * Moore * Mealy * Registered Output * FSM and Simulation * FSM and Synthesis * Combinational Logic * Combinational Logic * Example of a Multiplier * Differences in Synthesis * Sequential Logic * Advanced Synthesis * Controlling Synthesis * Master-Slave Flip-Flop * Why MSFF? * RS-FF * D-FF * JK-FF … text/html 2015-12-11T10:27:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/synthesis/what_is_synthesis?rev=1449829626&do=diff What is Synthesis? In general [What is Synthesis?] * Transformation of an abstract description into a more detailed description * “+” operator s transformed into a gate netlist * “if (VEC_A = VEC_B) then” is realized as a comparator which controls a multiplexer