https://www.vhdl-online.de/ 2026-04-28T19:08:21+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2016-02-17T22:29:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/delay_models?rev=1455748176&do=diff Delay Models Types of Delay Transport delay: * models the current flow through a wire (everything is transferred) [Transport Delay] Inertial delay: (default delay mechanism) * models spike-proof behavior ➔ a value is transferred only if it is active for at least 2 ns text/html 2015-11-18T22:16:43+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/design_verfication?rev=1447885003&do=diff Design Verification Waterfall Model [Waterfall Model] Cost/Effort analysis distribution of verification efforts: [Cost/Effort analysis] (ITRS 99 - Design Fig. 8) text/html 2016-02-09T19:59:16+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/file_io?rev=1455047956&do=diff File I/O Example Structure of a design [Structure of a design] * Which files will have to be recompiled if there is a change in the following files? (only minor changes, i.e. comments) * Entity of module C * Architecture of module D * Package PKG1 * Package PKG2 text/html 2016-05-18T22:49:31+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/lost_chapters?rev=1463611771&do=diff Testbenches after “Fundamentals”: Structure of a VHDL Testbench * Empty entity entity TB_TEST is end TB_TEST; * Declaration of the DUT * Connection of the DUT with testbench signals * Stimuli and clock generation (behavioural modelling) text/html 2016-06-21T11:36:03+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/notizen?rev=1466508963&do=diff Deutsche Notizen Testbenches Fundamentals Zur Verifikation der spezifizierten Funktionalität des entwickelten Bausteins verwendet man eine Testbench, die das DUT (Device Under Test) mit Stimuli versorgt und die erhaltenen Antworten analysieren oder abspeichern kann. Die Information für die Stimuligenerierung kann entweder aus einem externen File erfolgen oder fest in die Testbench integriert werden. Ein Simulator stellt die Signale in Waveforms dar, die der Designer mit den zu erwarteten Erge… text/html 2015-11-18T22:56:33+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/pagefooter?rev=1447887393&do=diff ---------- Chapters of System Design > Simulation * Design Verfication * Testbenches * Simulation Flow * File IO * Delay Models * Quiz text/html 2016-04-25T11:25:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/quiz?rev=1461583513&do=diff Quiz text/html 2015-12-11T16:10:02+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/simulation_flow?rev=1449850202&do=diff Signal Flow Fundamentals [Signal Flow] The simulation of a VHDL model operates in three phases. * Design elaboration * Specified elements are created * Signal initialisation * Starting values are assigned * Simulation is executed on command Elaboration text/html 2015-11-18T22:56:42+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/start?rev=1447887402&do=diff Simulation * Design Verfication * Testbenches * Simulation Flow * File IO * Delay Models * Quiz text/html 2015-12-11T16:43:13+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/simulation/testbenches?rev=1449852193&do=diff Testbenches Fundamentals Example of a testbench [Example of a testbench] * Stimuli transmitter to DUT (testvectors) * Needs not to be synthesizable * No ports to the outside * Environment for DUT * Verification and validation of the design * Several output methods