https://www.vhdl-online.de/ 2026-04-29T19:14:30+00:00 https://www.vhdl-online.de/ https://www.vhdl-online.de/_media/logo.png text/html 2016-06-22T11:53:33+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/design_components?rev=1466596413&do=diff Design Components Overview * Five basic design units, divided into two groups: * Primary units: * Entity [Entity] * Package * Configuration [Configuration] * Secondary units: * Package Body * Architecture [Architecture] * Each design unit has to be analysed and stored in a library text/html 2016-02-18T20:54:35+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/design_reuse?rev=1455828875&do=diff Design Reuse Overview [Design Reuse] Notes Reuse means to fall back on existing problem solutions. Every design engineer will try to apply previous VHDL code to the current situation. This is fairly simple because all details of the implementation are already known and consequently the code can be easily changed. text/html 2015-12-11T17:38:36+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/file_organisation?rev=1449855516&do=diff File Organisation Overview * Primary and secondary design units can be split into several files * Advantages of * Several Packages * Modularisation and reuse aspects (IEEE, corporate, project packages) * Separation of synthesizable from simulation only VHDL text/html 2016-05-18T23:21:06+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/lost_chapters?rev=1463613666&do=diff Name Spaces Use of Packages * Definitions of: * types, subtypes, constants, components and subprograms * Deferred constants: * constants, which are declared in the header of a package and are assigned a value in the body package P is constant C: integer; end P; text/html 2015-12-11T17:37:43+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/name_spaces?rev=1449855463&do=diff Name Spaces Introduction package PKG is constant C : integer := 1; end PKG; use work.PKG.all; entity ENT is end ENT; architecture RTL of ENT is signal C : integer := 8; begin -- only signal C is visible C <= 24; process variable C : integer := 9; begin -- only variable C is visible C := 42; for C in 0 to 5 loop -- only loop parameter C -- is visible ENT.C <= C; -- selected -- name end loop; ENT.C <= wo… text/html 2016-06-22T11:56:52+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/notizen?rev=1466596612&do=diff Deutsche Notizen File Organisation Overview In VHDL gibt es mehrere Möglichkeiten, um einen hierarchischen Entwurf zu implementieren. Die Sprache stellt hierfür vorallem die Philosophie von Entity/Architektur Paaren und deren Einbindung über Komponenten zur Verfügung. Dies führt zu einer strikten Trennung von Schnittstelle und Innenleben. Mit der Hilfe von Packages, Bibliotheken und einem verinheitlichten Codierstil ist es möglich, auch sehr große Entwürfe, die auf einige Textdateien aufgetei… text/html 2015-11-17T15:43:08+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/pagefooter?rev=1447774988&do=diff ---------- Chapters of System Design > Project Management * File Organisation * Design Components * Name Spaces * Design Reuse * Quiz text/html 2016-04-25T11:27:14+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/quiz?rev=1461583634&do=diff Quiz text/html 2015-11-17T15:42:56+00:00 Anonymous (anonymous@undisclosed.example.com) https://www.vhdl-online.de/courses/system_design/project_management/start?rev=1447774976&do=diff Project Management * File Organisation * Design Components * Name Spaces * Design Reuse * Quiz