Introduction

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VHDL-AMS (Very High Speed Integrated Circuit Hardware Description Language for Analog and Mixed Signals) is a computer language to simulate analog and digital systems simultaneously. It is an extension to IEEE VHDL 1076-1993 and is called IEEE VHDL 1076.1-1998. The language is defined at the LRM (Language Reference Manual).

The number of the single chips on a board declines permanent because of the all times new technological possibilities. Thus the mostly devided 'analog' and 'digital' electronic components on a chip get together. Because of this rising integration the interfaces between the analog and digital function chips get lost. So it is desireable to simulate the complete analog and digital system at once. From there the since many years often used VHDL 1076-1993 gets extended for an analog part (VHDL 1076.1-1998) without loosing functions for the digital simulation. The simulation on a single kernel is possible. The general synthesis of analog / mixed-signal circuits is not expected in the next few years because of the high multifariousness.

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One of the most important field of application is the simulation of ASIC's (Application Specific Integrated Circuits) and of complete (physical) systems. Emphasizeable is the operational area for mobile communication (handy) and video processing, where analog and digital signals are very strong concatenationed.

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Discrete (digital) systems change their states mercurial in countable moments. In contrast to is the state change at continuous (analog) systems. It executes steady and is every time possible. So an exact analog simulation between any two moments would take infinite calculation steps. The balance between accuracy and calculation effort is a central problem at the simulation of analog signals. Mixed signal simulation claims a synchronization of both (analog and digital) signal types to re-create the real behavior.

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The simulation cycle is very complex. So only the simplified graph will be introduced.

The simulation cycle starts with initialize the analog signals and determine the time of the next analog calculation Tc (current time) and the time of the next digital simulation Tn (next time). So long as no digital event occurs, analog equations get calculated and the time of the next analog calculation gets determined. At a digital event, by expired digital time (Tn = 0) or an analog to digital event, all signals get refreshed. Then the sensitive processes are executed (first nonpostponed then postponed). After the time of the next digital event is determined. The simulation is completed, if this time in 0.0. If this time is shorter than Tc, the digital cycle will start again, else the analog calculations continue.

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It is possible to simulate networks as well as signal flows of a system. At a signal flow simulation the signal flow is directed. The signal of any path has no backlash on the previous system components. At a network simulation you have no signal flow direction, because a backlash inside the network is possible. The backlash on a cause can influence the signals of the cause. Thus the simulation of networks is more complex than the simulation of signal flows.

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It is a conservative system if the energy theorem valids. At networks the KIRCHHOFF rules are valid, which obey the Energieerhaltungssatz. So networks are conservative systems. But the simulation of signal flows is also possible, that non - conservative systems are simulateable, too.

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Till now, the simulation of analog and digital systems is possible but only limited. The analog simulator SABER (in MAST) from Analogy offers a small area for digital simulation. But it is very restricted for digital simulation, i. e. loops or busses are not programmable on the high level of VHDL.

Co-simulators, that are two separate simulators, one for the analog simulation and the other for the digital simulation, are used, too. The disadvantage is, that you simulate on two simulation kernels. That is expensive and it takes too much time. Their function is based on the master / slave principle.