====== LAB 2: Extending the Multiplexer ======
===== Synopsis =====
As the module will be used to multiplex single digit values later on, the bus widths need to be adjusted. This is easily done by specifying a range for all data signals which are of type integer. Additionally, error conditions shall also be signaled to the user via the camera display. Therefore, an additional control input named ERROR is needed. The following figure shows the updated schematic:

{{:vhdl_workshop:workshop_extmultiplexer.svg?nolink&500|The enhanced multiplexer}}

==== Behaviour ====
DISP_PHOTO shall be set to ’10’ when the ERROR signal is active. Otherwise, the multiplexer behaviour shall not be changed, i.e. the output shall be equal to the EXP_TIME input when the control signal SHOW_TIME is 1. Else, DISP_PHOTO shall be set to NO_PICS.

==== Data types ====
All data signals (NO_PICS, EXP_TIME, DISP_PHOTO) shall be of type **integer** with a range of valid values from 0 to 10. The new control signal ERROR shall be of type **std_ulogic**, as the SHOW_TIME signal.

==== To do ====
  * Modify the existing multiplexer model.
  * Compile your design.
  * Modify the testbench according to the changes of the DISP_MUX interface and create new stimuli to verify the proper behaviour.
  * Compile the testbench.
  * Run the simulation.
  * Synthesize the model.

===== Implementation =====
<code vhdl DISP_MUX.VHD>
library ieee;
use ieee.std_logic_1164.all;

entity DISP_MUX is
  port(EXP_TIME   : in integer; -- range needed
       NO_PICS    : in integer; -- range needed
       SHOW_TIME  : in std_ulogic;
       -- add ERROR port
       DISP_PHOTO : out integer;); -- range needed
end DISP_MUX;

architecture RTL of DISP_MUX is
begin
  process(NO_PICS, EXP_TIME...) -- complete sensitivity list!!
  begin
    -- add ERROR condition
    if SHOW_TIME = '1' then
      -- output = exposure time
    else
      -- output = picture count
    end if;
  end process;
end RTL;
</code>

===== Testbench =====
<code vhdl TB_DISP_MUX.VHD>
library ieee;
use ieee.std_logic_1164.all;

entity TB_DISP_MUX is
end TB_DISP_MUX;

architecture TEST of TB_DISP_MUX is
  component DISP_MUX
    port(EXP_TIME   : in integer range 0 to 10;
         NO_PICS    : in integer range 0 to 10;
         SHOW_TIME  : in std_ulogic;
         -- add ERROR port
         DISP_PHOTO : out integer range 0 to 10);
  end component;
  
  signal W_EXP_TIME   : integer range 0 to 10 := 0;
  signal W_NO_PICS    : integer range 0 to 10 := 0;
  signal W_SHOW_TIME  : std_ulogic := '0';
  signal W_ERROR      : -- type???
  signal W_DISP_PHOTO : integer range 0 to 10;
  
begin
  DUT : DISP_MUX
    port map (
      EXP_TIME   => W_EXP_TIME,
      NO_PICS    => W_NO_PICS,
      SHOW_TIME  => W_SHOW_TIME,
      ERROR      => W_ERROR,
      DISP_PHOTO => W_DISP_PHOTO);
      
  STIMULI : process
  begin
    -- DISP_PHOTO = 0
    wait for 30 ns;
    
    W_NO_PICS <= 2;
    W_EXP_TIME <= 5;
    -- DISP_PHOTO = 2
    wait for 20 ns;
    
    W_NO_PICS <= 10;
    -- DISP_PHOTO = 10
    wait for 20 ns;
    
    W_SHOW_TIME <= '1';
    -- DISP_PHOTO = 5
    wait for 20 ns;

    W_EXP_TIME <= 6;
    W_NO_PICS <= 4;
    -- DISP_PHOTO = 6
    wait for 20 ns;
    
    W_SHOW_TIME <= '0';
    -- DISP_PHOTO = 4
    wait for 20 ns;
    
    W_ERROR <= '1';
    -- DISP_PHOTO = 10
    wait for 20 ns;
    
    W_SHOW_TIME <= '1';
    -- no changes
    wait for 20 ns;
    
    W_ERROR <= '0';
    -- DISP_PHOTO = 6
    wait for 20 ns;
    
    W_SHOW_TIME <= '0';
    -- DISP_PHOTO = 4
    wait for 20 ns;
    wait;
  end process STIMULI;
end TEST;

configuration CFG_TB_DISP_MUX of TB_DISP_MUX is
  for TEST
  end for;
end CFG_TB_DISP_MUX;
</code>