====== Subprogram body ======
===== subprogram_body =====
<code vhdl>
subprogram_specification is
     subprogram_declarative_part
begin
    subprogram_statement_part
end [ subprogram_kind ] [ designator ] ;
</code>

===== Parent =====
  * entity_declarative_part
  * architecture_declarative_part
  * package
  * package_body
  * block_declarative_part
  * process_declarative_part

===== Further definitions =====
==== subprogram_specification ====
''procedure [[.:bnf#designator]] [ ( [[.:bnf#formal_parameter_list]] ) ]''

''[ pure | impure ] function [[.:bnf#designator]] [ ( [[.:bnf#formal_parameter_list]] ) ]'' \\
''return [[.:bnf#type_mark]]''

==== subprogram_declarative_part ====
''{ [[.:bnf#subprogram_declarative_item]] }''

==== subprogram_statement_part ====
''{ [[.:bnf#sequential_statement]] }''

==== subprogram_kind ====
  * procedure
  * function

==== designator ====
  * [[.:bnf#identifier]]
  * [[.:bnf#operator_symbol]]

===== Comment =====
  * The declaration of a subprogram is optional. The subprogram specification can act as the declaration.
  * //Shared variables// must not be declared in subprograms.
  * A "foreign subprogram" is a subprogram with the attribute **FOREIGN** . The value of the attribute (a string) can contain implementation specific information for linking the external program (see example below).
  * A pure function must not contain a reference to an explicitly declared file object.
  * A pure function must not be the parent of an impure function.

===== Examples =====
Definition of the procedure //thank_you// .

If the condition //false// is not fulfilled "Thank You !" is reported as //note// in the severity level.
<code vhdl>
PROCEDURE thank_you IS
BEGIN
   ASSERT false
   REPORT "Thank You !"
   SEVERITY note ;
END thank_you ;
</code>

----

Definition of the function //convert// with the transfer value //B// and the result type //fuzzy_bit// .

In the If-loop the variable //v// is assigned the value High or Low depending on the value of //B// .

//v// is transferred as transfer value.
<code vhdl>
FUNCTION convert(B : Bit ) RETURN fuzzy_bit IS
   VARIABLE v : fuzzy_bit ;
BEGIN
   IF B = '1' THEN
      v := High ;
   ELSE
      v := Low ;
   END IF ;
   RETURN v ;
END convert ;
</code>

----

Definition of the procedure //regist// with the transfer values of the signals //D// , //CK// and //Q// .

Within the endless loop (LOOP) a register is declared which takes on the value of input //D// from output //Q// at the positive clock-edge with a delay of 1 ns.
<code vhdl>
PROCEDURE regist(
   SIGNAL D : IN Bit ;
   SIGNAL CK : IN Bit ;
   SIGNAL Q : OUT Bit ) IS
BEGIN
   LOOP
      WAIT ON CK ;
      IF CK = '1' THEN
         Q <= D AFTER 1 ns ;
      END IF ;
   END LOOP ;
END regist ;
</code>

----

Definition of the procedure //p//; transfer values of the variable //COL// and the constant //C// .

The subtype //primary_color// is declared from the type //colour// with a range of //yellow// to //red// (from the enumeration type //colour// ). The variables //X// , //Y// and //Z// are declared.
<code vhdl>
PROCEDURE p(
   VARIABLE COL : INOUT color ;
   CONSTANT C : IN choice ) IS
   SUBTYPE primary_color IS
      color RANGE yellow TO red ;
VARIABLE X, Y, Z : primary_color ;
BEGIN

...
...

END p ;
</code>

----

The external function //exfunc// is declared.

The attribute //FOREIGN// of //exfunc// gets (simulator-) program specific information.
<code vhdl>
FUNCTION exfunc RETURN INTEGER ;

ATTRIBUTE FOREIGN OF exfunc FUNCTION
IS "C:modellib.so.0.1 ELAB:mod_lab";
</code>