====== Signal declarations ======
===== signal_declaration =====
<code vhdl>
signal identifier_list : subtype_indication [ signal_kind ] [ := expression ] ;
</code>

===== Parents =====
  * entity_declarative_part
  * architecture_declarative_part
  * package
  * block_declarative_part
  * procedure_declarative_part

===== Further definitions =====
==== identifier_list ====
''[[.:bnf#identifier]] {, [[.:bnf#identifier]] }''

==== subtype_indication ====
''[ resolution_function_ [[.:bnf#name]] ] [[.:bnf#type_mark]] [ [[.:bnf#constraint]] ]''

==== signal_kind ====
  * register
  * bus

==== expression ====
  * [[.:bnf#relation]] { and relation }
  * relation { or relation }
  * relation { xor relation }
  * relation [ nand relation ]
  * relation [ nor relation ]
  * relation { xnor relation }

The signals declared with **REGISTER** or **BUS** are 'guarded signals'.

'Guarded signals' have to be 'resolved signals'.

Guarded signal assignments have the following meaning for 'guarded signals':

<code vhdl>
IF guard_expression THEN
     sig_name <= sig_waveform ;
ELSE
     sig_name <= NULL ;
END IF ;
</code>

The assignment of **NULL** to the signal //sig_name// means that the driver of this signal assignment is switched off. This has the following consequences for the 'resolved signal':
      * If not all drivers were switched off the resulting signal is only determined by the drivers which were not switched off.
  *     If all drivers were switched off the last available signal value is kept in case of the signal declaration **REGISTER** .
  *     If all drivers were switched off the default value stated in the `resolution function` is used in case of the signal declaration **BUS** .

The signal driver is switched off immediately, i.e. without delay, after the //guard_expression// has taken on the value //false// except if an explicit delay time was planned to be given to the signal by the disconnection-statement after it was declared a controlled signal. An extensive example on this can be found in the chapter [[.:Disconnection specification]].

===== Examples =====
The signals //clk_1// and //clk_2// of the physical type //time// are declared.
<code vhdl>
SIGNAL clk_1, clk_2 : time ;
</code>

----

  * The signal //address// of the type //bit8// is declared and initialized with the value "00110110".
  * The signal //bittab// is declared by the type //bit_vector// and initialized with the value "000111Z1Z".
  * The signal //tab// is declared by the type //table_type// and initialized with the values 2, 3, 4, -2 and 0.

<code vhdl>
SIGNAL address : bit8 := "00110110" ;

SIGNAL bittab : bit_vector(1 TO 9)
      := ( 1 TO 3 => '0', 7 | 9 => 'Z',
          OTHERS => '1' ) ;

SIGNAL tab : table_type( 0 TO 4 )
      := ( 2, 3, 4, -2, 0 ) ;
</code>

----

The signal //address_bus// is declared as a guarded signal (BUS) of the type //resolved_bit_vector// and initialized with the value "10011001".
<code vhdl>
SIGNAL address_bus : resolved_bit_vector
      BUS := "10011001"; 
</code>

----

The signal //resolved_s// is declared as a guarded signal (REGISTER) of the type //zbit// . In addition to that the signal is also assigned a [[.:resolution function]] //resolution_function// .
<code vhdl>
SIGNAL resolved_s : resolution_function
      zbit REGISTER ;
</code>