====== Signal assignment  ... <= ..." ======
===== signal_assignment_statement =====
<code vhdl>[ label : ] target <= [ delay_mechanism ] waveform ;</code>

===== Parents =====
  * function_statement_part
  * procedure_statement_part
  * process_statement_part

===== Further definitions =====
==== delay_mechanism ====
<code vhdl>transport</code>

''[ **reject** //time// _[[.:bnf#expression]] ] **inertial**''

==== target ====
  * [[.:bnf#name]]
  * [[.:bnf#aggregate]]

==== waveform ====
''[[.:bnf#waveform_element]] { , waveform_element }''
<code vhdl>unaffected</code>

===== Comments =====
The keyword **unaffected** is allowed only in concurrent signal assignments.

The default delay mechanism is **inertial** .

With **transport** all pulses are transmitted.

With **inertial** only those pulses are transmitted, with width is greater than the a given limit. This limit is given by the value after **reject** or the first time value in the waveform.

The value after **reject** must not be greater than the first time value of the waveform.

===== Examples =====
The value of //B// is assigned to signal //A// after 5 ns.

In the first example the inertial delay model is used, in the second example the transport delay model is used.
<code vhdl>
A <= B AFTER 5 ns;

A <= TRANSPORT B AFTER 5 ns;
</code>

----

A waveform is assigned to signal //data// , according to which //data// receives the value //2// after 1 ns, the value //4// after 3ns and the value //10// after 8ns.
<code vhdl>
data <= 2 AFTER 1 ns,
       4 AFTER 3 ns,
      10 AFTER 8 ns;
</code>

----

Signal A is assigned the result of the function //my_function// by the inertial delay model

In the first example this happens after 5ns; in the second and third example this happens after a time which is determined by the constant delay. In the third example the value //0// is transferred to A 2ns after the preceding assignment.
<code vhdl>
A <= my_function(data, 4) AFTER 5 ns;

A <= my_function(data, 4) AFTER delay;

A <= my_function(data, 4) AFTER delay,
      0 AFTER delay + 2 ns;
</code>

----

These assignments are equivalent. The value of //input// is driven to //output// with a delay of 6 ns. Pulses smaller 6 ns are suppressed.
<code vhdl>
ouptut <= input AFTER 6 ns;
output <= INERTIAL input AFTER 6 ns;
output <= REJECT 6 ns INERTIAL input
           AFTER 6 ns;
</code>

----

Here the pulse rejection limit is smaller than the first time expression in the waveform. All pulses smaller 3 ns are suppressed.
<code vhdl>
output1 <= REJECT 3 ns INERTIAL input1
            AFTER 6 ns;
output2 <= REJECT 3 ns INERTIAL input2
            AFTER 6 ns,
            NOT input2 AFTER 12 ns;
</code>

----

The signal assignments to //output1// and //ouput2// are equivalent to those of //ouput3// and //output4// .

No pulses are suppressed.
<code vhdl>
output1 <= TRANSPORT input1
           AFTER 6 ns;
output2 <= TRANSPORT input2
           AFTER 6 ns,
           NOT input2 AFTER 12 ns;

output3 <= REJECT 0 ns INERTIAL input1
          AFTER 6 ns; output4 <= REJECT 0 ns INERTIAL input2
          AFTER 6 ns
          NOT input2 AFTER 12 ns;
</code>

----

In VHDL'87 one had to choose the above assignments. Both variants are equivalent.
<code vhdl>
-- VHDL'87
   sig2 <= input AFTER 3 ns;
   output <= TRANSPORT sig2
             AFTER 9 ns;
-- VHDL'93
   output <= REJECT 3 ns INERTIAL
             input AFTER 12 ns;
</code>