====== Generate statement  ======
===== generate_statement =====
<code vhdl>
generate _label :
  generation_scheme generate
      [ { block_declarative_item }
  begin ]
      { concurrent_statement }
  end generate [ generate _label ] ;
</code>

===== Parents =====
  * architecture_statement_part
  * block_statement_part

===== Further definitions =====
==== label ====
  * [[.:bnf#identifier]]

==== generation_scheme ====
''**for** //generate// _[[.:bnf#parameter_specification]]''

''**if** [[.:bnf#condition]]''

==== block_declarative_item ====
  * [[.:bnf#subprogram_declaration]]
  * [[.:bnf#subprogram_body]]
  * [[.:bnf#type_declaration]]
  * [[.:bnf#subtype_declaration]]
  * [[.:bnf#constant_declaration]]
  * [[.:bnf#signal_declaration]]
  * //shared// _[[.:bnf#variable_declaration]]
  * [[.:bnf#file_declaration]]
  * [[.:bnf#alias_declaration]]
  * [[.:bnf#component_declaration]]
  * [[.:bnf#attribute_declaration]]
  * [[.:bnf#attribute_specification]]
  * [[.:bnf#configuration_specification]]
  * [[.:bnf#disconnection_specification]]
  * [[.:bnf#use_clause]]
  * [[.:bnf#group_template_declaration]]
  * [[.:bnf#group_declaration]]

==== concurrent_statement ====
  * [[.:bnf#block_statement]]
  * [[.:bnf#process_statement]]
  * [[.:bnf#concurrent_procedure_call_statement]]
  * [[.:bnf#concurrent_assertion_statement]]
  * [[.:bnf#concurrent_signal_assignment_statement]]
  * [[.:bnf#component_instantiation_statement]]
  * [[.:bnf#generate_statement]]

===== Comment =====
In VHDL'87 there was no declarative region.

===== Examples =====
This generate-statement forms a parallel chain out of the two components //comp_1// and //comp_2// with a length of 5.
<code vhdl>
lbl_1 :
   FOR i IN 1 TO 5 GENERATE
      c1 : comp_1 PORT MAP
         ( ck => clock,
            d => a(i),
            q => a(i+1) ) ;
      c2 : comp_2 PORT MAP
         ( ck => clock, d => a(i) ) ;
   END GENERATE ;
</code>

----

If the generic //n// is bigger than 0 the signal assignments take effect and the component //my_comp// is instantiated.
<code vhdl>
lbl_2 :
   IF n > 0 GENERATE
      sig_1 <= '1' AFTER 5 ns ;
      sig_2 <= sig_1 AFTER 2 ns ;
      c : my_comp PORT MAP (a, b, c) ;
   END GENERATE ;
</code>

----

Example of a chained generate-statement.

Within the external statement several components are instantiated irrespective of the counter variable //i// .
<code vhdl>
cadd :
   FOR i IN 1 TO n GENERATE
      cb : IF i = 1 GENERATE
         add_b : add_begin PORT MAP
                          ( ... ) ;
      END GENERATE ;
      cm : IF i > 1 AND i < n GENERATE
         add_m : add_middle PORT MAP
                           ( ... ) ;
      END GENERATE ;
      ce : IF i = n GENERATE
         add_e : add_end PORT MAP
                         ( ... ) ;
      END GENERATE ;
   END GENERATE cadd ;
</code>

----

Example of the wide range of applications for the generate statement.

In order to make them easier to survey the chained generate-statements at label //l2// were duplicated at label //l6// with an altered **IF** -condition.

The generate-statement at label //l8// can also be stated within the generate-statement at label //l3// .
<code vhdl>
b : BLOCK
BEGIN

  l1 : cell PORT MAP ( top, bottom,
                       a(0), b(0) ) ;

  l2 : FOR i IN 1 TO 3 GENERATE
    l3 : FOR j IN 1 TO 3 GENERATE
      l4 : IF i + j > 4 GENERATE
        l5 : cell PORT MAP ( a(i-1),
                 b(j-1), a(i),b(j));
      END GENERATE ;
    END GENERATE ;
  END GENERATE ;


  l6 : FOR i IN 1 TO 3 GENERATE
    l7 : FOR j IN 1 TO 3 GENERATE
      l8 : IF i + j < 4 GENERATE
        l9 : cell PORT MAP ( a(i+1),
               b(j+1), a(i), b(j));
      END GENERATE ;
    END GENERATE ;
  END GENERATE ;

END BLOCK b ;
</code>