====== File declarations ======
===== file_declaration =====
<code vhdl>file identifier_list : subtype_indication [ file_open_information ] ;</code>

===== Parents =====
  * entity_declarative_part
  * architecture_declarative_part
  * package
  * package_body
  * block_declarative_part
  * function_declarative_part
  * procedure_declarative_part
  * process_declarative_part

===== Further definitions =====
==== identifier_list ====
''[[.:bnf#identifier]] {, [[.:bnf#identifier]] }''

==== subtype_indication ====
''[ resolution_function_ [[.:bnf#name]] ] [[.:bnf#type_mark]] [ [[.:bnf#constraint]] ]''

==== file_open_information ====
''[ open file_open_kind_ [[.:bnf#expression]] ] is [[.:bnf#file_logical_name]]''

===== Comments =====
File declarations are incompatible between VHDL'87 and VHDL'93!

The standard does not define what happens if more than one logical files access the same physical file, specifically for different access modes.

===== Examples =====
==== VHDL'87 ====
//simulation_output// is declared as a (virtual) output file of the type //my_file_type// with the physical path and name /home/usr2/sim.res.
<code vhdl>
FILE simulation_output : my_file_type IS OUT "/home/usr2/sim.res" ;
</code>

----

//rom_content// is declared as a (virtual) input file of the type //rom_file_type// with the physical name "rom2048.txt".
<code vhdl>
FILE rom_content : rom_file_type IS IN "rom2048.txt" ;
</code>

----

//input// and //output// are predefined files of the type //text// with the physical names //std_input// and //std_output//.
<code vhdl>
FILE input : text IS IN "std_input";
FILE output : text IS OUT "std_output";
</code>

----

//sim_output// is declared as a (virtual) output file (mode **IN** is default) of the type //my_file_type// with the physical path and name /home/usr3/sim.trc.
<code vhdl>
FILE sim_output : my_file_type IS OUT "/home/usr3/sim.trc" ;
</code>

==== VHDL'93 ====
//nowhere// is declared as (virtual) file of type //my_file_type// but without explicitly open it.
<code vhdl>FILE nowhere : my_file_type ;</code>

----

//simulation_input// is declared as (virtual) file of type //my_file_type// with the physical path and name /home/usr2/sim.in. At Elaboration, FILE_OPEN(simulation_input, "/home/usr2/sim.res") is called implicit with the default READ-MODE.
<code vhdl>
FILE simulation_input : my_file_type IS "/home/usr2/sim.res" ;
</code>

----

//simulation_output// is declared as (virtual) output file of type //my_file_type// with the physical path and name /home/usr2/sim.res.
<code vhdl>
FILE simulation_output : my_file_type OPEN WRITE_MODE IS "/home/usr2/sim.res" ;
</code>