====== Entity ======
===== entity_declaration =====
<code vhdl>
entity identifier is
    entity_header
    entity_declarative_part
[ begin
    entity_statement_part ]
end [ entity ] [ entity _simple_name ] ;
</code>

===== Further definitions =====
==== identifier ====
  * [[.:bnf#basic_identifier]]
  * [[.:bnf#extended_identifier]]

==== entity_header ====
''[ //formal// _[[.:bnf#generic_clause]] ]'' \\
''[ //formal// _[[.:bnf#port_clause]] ]''

==== entity_declarative_part ====
''{ [[.:bnf#entity_declarative_item]] }''

==== entity_statement_part ====
''{ [[.:bnf#entity_statement]] }''

==== simple_name ====
  * [[.:bnf#identifier]]

===== Examples =====
Example of a testbench which possesses neither inputs nor outputs.
<code vhdl>
ENTITY testbench IS
END testbench ;
</code>

----

Entity for a 2-Bit-fulladder.
  * //X// , //Y// and //Cin// are Bit type inputs.
  * //Cout// and //Sum// are Bit type outputs.
<code vhdl>
ENTITY fulladder IS
   PORT (X,Y,Cin   : IN  Bit;
         Cout, Sum : OUT Bit);
END fulladder ;
</code>

----

Entity with several features:
  * Definition of a parameter //m// .
  * //b1// and //b2// are inputs (Bits), //b3// is an output-vector with the width //m// .
  * Definition of type //byte// as a bit-vector.
  * Integrating the objects from the package //timing_library// . Definition and initialisation of a constant setup time.

Definition of procedure //init// with signal transfer. 
Seizing of //b4// with several `1` is carried out only after //delay// .

Instructions within the entity:
  * If the condition which is to be checked is not fulfilled an error is reported. //Error// is the severity level.
  * A passive //procedure// (signal assignments in the entity are not allowed!) with //b4// and //delay// as transfer values is called.

<code vhdl>
ENTITY big_example IS
   GENERIC (m : Positive);
   PORT (b1,b2 : IN Bit;
         b3: OUT Bit_Vector(1 to m));
   TYPE byte IS ARRAY (1 TO 8) OF Bit;
   USE work.timing_library.all;
   CONSTANT setuptime : Time := 12 ns;


   PROCEDURE init ( SIGNAL b4 : OUT byte) IS
   BEGIN
      b4 <= ( OTHERS => '1') AFTER delay;
   END init;

BEGIN
   ASSERT b4' DELAYED'STABLE (5 ns)
      REPORT "Error occured!"
      SEVERITY Error;
   passive_procedure(b2,delay);
END big_example ;
</code>