====== Elaboration of a statement part ======
The elaboration rules are valid for all statement parts except these of an architecture with the attribute **FOREIGN** . These are elaborated implementation dependent.

===== Block statements =====
The block`s beginning, its declarative part and its statement part are elaborated successively:
  * Begin (if present)
<code vhdl>
my_block : BLOCK (enable = '1')
PORT (farbe_1, farbe_2, select : std_ulogic;
                       auswahl : std_ulogic BUS);
PORTMAP (farbe_1 => color(0),
         farbe_2 => color(1),
         auswahl => point);
</code>
  * Declarative part
<code vhdl>SIGNAL inter : std_ulogic;</code>
  * Statement part
<code vhdl>
BEGIN
    inter   <= farbe_1 WHEN select = '0' ELSE farbe_2;
    auswahl <= GUARDED inter;
END BLOCK my_block;
</code>

A block statement can be elaborated under the control of a configuration declaration. An enclosed block configuration can generate a number of additional implicitly defined specifications which are used when the corresponding block statement is elaborated and which are thus elaborated at the same time.

Each of these implicit specifications consists of that configuration`s specification which is implied by the component configurations within the block configuration. 

{{:vhdl_reference_93:vhdlreference_elaborationblockstatement.svg?nolink&700|Elaboration of a Block Statement}}

===== Generate-statement =====
The generate-statement is replaced by copies of block statements whose statement part consists of the concurrent statements contained in the generate-statement. Each block statement is afterwards elaborated.

{{:vhdl_reference_93:vhdlreference_elaborationgeneratestatement.svg?nolink&500|Elaboration of a Generate Statement}}

With a **FOR** generate-statement the individual value range is elaborated. Then a block statement is generated for every value within that range. This statement has the following characteristics:
  * The names of the block statement and of the generate-statement are the same.
  * The declarative part contains a constant-declaration which declares a constant under the name of the generate parameter. The constant`s value is equal to that of the generate parameter; its type is determined by the base type of the generate parameter`s value range.
  * The statement part contains a copy of the concurrent statements from the generate-statement.

With an **IF** generate-statement the logic expression is calculated. If the expression takes on the value `true` a block statement is generated which has the following characteristics:
  * The same names are valid for both the block and the generate-statement.
  * The block`s declarative part is empty.
  * The statement part contains a copy of the concurrent statements (see above).

===== Component instantiation statements =====
The component either has to be fully linked to an entity determined by an entity-declaration and an architecture, or it has to be linked to an entity`s configuration. Both the implicitly defined block statement, which describes the component`s instant, and the block statement, which is also implicit and refers to the entity mentioned above, are elaborated.

===== Other concurrent statements =====
All other concurrent statements are either process statements or statements for which an equal process statement exists. Elaboration comprises the following steps:
  * The declarative part of the process is elaborated.
  * The drivers required by the process statement are provided.
  * The initial process, which is defined by the default values of scalar signals, is inserted into the corresponding driver.

In the elaboration of all concurrent signal-assignment statements and of all concurrent assertion-statements an equal process statement is generated and then elaborated.

{{:vhdl_reference_93:vhdlreference_elaborationotherconcurrentstatement.svg?nolink&600|Elaboration of other concurrent statement}}