====== Disconnection specification ======
===== disconnection_specification =====
<code vhdl>disconnect guarded_signal_specification after time _expression ;</code>

===== Parents =====
  * entity_declarative_part
  * architecture_declarative_part
  * package
  * block_declarative_part

===== Further definitions =====
==== guarded_signal_specification ====
''guarded _[[.:bnf#signal_list]] : [[.:bnf#type_mark]]''

==== expression ====
  * [[.:bnf#relation]] { and relation }
  * relation { or relation }
  * relation { xor relation }
  * relation [ nand relation ]
  * relation [ nor relation ]
  * relation { xnor relation }

===== Examples =====
//a// is declared as a guarded signal of the type **[[.:Signal declarations|REGISTER]]** . If during simulation a driver for the signal //a// is deactivated this happens with a delay of 1ns.
<code vhdl>
SIGNAL a : resolved_type REGISTER ;
DISCONNECT a : resolved_type AFTER 1 ns;
</code>

----

//sig1// , //sig2// and //sig3// are declared as guarded signals of the type **[[.:Signal declarations|REGISTER]]** . During simulation the drivers for //sig1// are switched off with a delay of 5 ns and those of the other signals with a delay of 8 ns.
<code vhdl>
SIGNAL sig1, sig2, sig3 :
      resolved_bit REGISTER ;
DISCONNECT sig1 : resolved_bit
      AFTER 5 ns ;
DISCONNECT OTHERS :
      resolved_bit AFTER 8 ns ;
</code>

----

//bus_a// and //bus_b// are declared as guarded signals of the type **[[.:Signal declarations|bus]]** . During simulation the drivers for both signals are switched off with a delay of 6ns ( //delay// + 1 ns).
<code vhdl>
CONSTANT delay : time := 5 ns ;
SIGNAL bus_a, bus_b :
      resolved_zbit_vector32 BUS ;
DISCONNECT ALL : resolved_zbit_vector32
      AFTER delay + 1 ns ;
</code>

----

In the **PACKAGE** //fourval// a four-valued logic //mvl4// and a corresponding vector are defined.

The function //resolved// is declared. Consequently a 'resolved signal' can be derived as a **SUBTYPE** .

In the **PACKAGE BODY** the function //resolved// is described.

  * If the input signal //choice// changes to //1// the signal driver of the first block is activated and passes the first input signal on to the output after 20 ns.
  * If //choice// changes to //2// the second block passes the second input signal on the output after 18ns.
  * As the first signal driver switches off only after 25 ns both drivers are active simultaneously for 7ns. The resulting signal is determined by the 'resolution function' of the output signal.
  * If //choice// changes to a value other than //1// or //2// the last active driver switches off after 25 ns and the output signal changes to its default value (in this case 'Z') as it is declared as a **[[.:Signal declarations|bus]]** .
  * If it were declared as a **[[.:Signal declarations|REGISTER]]** the last signal value would be kept.

<code vhdl>
PACKAGE fourval IS
   TYPE mvl4 IS ('X','0','1','Z') ;
   TYPE mvl4_vector IS ARRAY
         (natural RANGE <>) OF mvl4 ;
   FUNCTION resolved (a: mvl4_vector)
         RETURN mvl4 ;
   SUBTYPE mvl4_r IS resolved mvl4 ;
END fourval ;

PACKAGE BODY fourval IS
   FUNCTION resolved (a: mvl4_vector)
         RETURN mvl4 IS
      VARIABLE result : mvl4 := 'Z' ;
      -- Defaultwert: 'Z'
   BEGIN
      ...
      RETURN result ;
   END resolved ;
END fourval ;


USE work.fourval.ALL ;
ENTITY mux_2_1 IS
PORT (in_signals : IN
   mvl4_vector (1 TO 2) ;
      choice     : IN integer ;
      out_signal : OUT mvl4_r BUS ) ;
END mux_2_1 ;

ARCHITECTURE with_guards OF mux_2_1 IS
   DISCONNECT out_signal : mvl4_r
              AFTER 25 ns ;
BEGIN

   choice_1 : BLOCK (choice = 1)
   BEGIN
     out_signal <= GUARDED
        in_signals(1) AFTER 20 ns ;
   END BLOCK ;

   choice_2 : BLOCK (choice = 2)
   BEGIN
      out_signal <= GUARDED in_signals(2)
            AFTER 18 ns ;
   END BLOCK ;

END with_guards ;
</code>