====== Block ======
===== block_statement =====
<code vhdl>
block _label :
  block [ ( guard _expression ) ] [ is ]
      block_header
      block_declarative_part
  begin
       block_statement_part
  end block [ block _label ] ;
</code>

===== Parents =====
  * architecture_statement_part

===== Further definitions =====
==== label ====
  * [[.:bnf#identifier]]

==== expression ====
  * [[.:bnf#relation]] { and relation }
  * relation { or relation }
  * relation { xor relation }
  * relation [ nand relation ]
  * relation [ nor relation ]
  * relation { xnor relation }

==== block_header ====
''[ [[.:bnf#generic_clause]] \\
  [ [[.:bnf#generic_map_aspect]] ; ] ] \\
[ [[.:bnf#port_clause]] \\
  [ [[.:bnf#port_map_aspect]] ; ] ]''

==== block_declarative_part ====
''{ [[.:bnf#block_declarative_item]] }''

==== block_statement_part ====
''{ [[.:bnf#concurrent_statement]] }''

===== Examples =====
This simple block has a label and a delayed signal assignment in the statement part.
<code vhdl>
b : BLOCK
BEGIN
   s <= '1' AFTER 2 ns ;
END BLOCK b ;
</code>

----

This block has an additional header in which the signal //int// is declared.
<code vhdl>
c : BLOCK
   SIGNAL int : bit_vector( 1 TO 3 )
                := "010" ;
BEGIN
   s <= int AFTER 5 ns ;
END BLOCK c ;
</code>

----

In this block a controlled signal assignment is used. If the condition //clock = '1'// is not fulfilled the signal assignment is not carried out.
<code vhdl>
latch : BLOCK ( clock = '1' )
BEGIN
   latch_output <= GUARDED
         latch_input AFTER 1 ns ;
END BLOCK latch ;
</code>

----

This block has separate in- and outputs which are linked to the overriding signals by the **PORT MAP** .
<code vhdl>
lbl : BLOCK
   PORT ( a, b : INOUT bit ) ;
   PORT MAP ( a => s1, b => s2 ) ;
BEGIN
   b <= a AFTER 1 ns ;
   a <= b AFTER 1 ns ;
END BLOCK lbl ;
</code>