====== COUNTERS library ======
The COUNTERS library contains the most common used counters and consists of the following 6 generic components:
* [[.:counters#buNar]]: N-bit binary up counter with asynchronous reset
* [[.:counters#bdNsr]]: N-bit binary down counter with synchronous reset
* [[.:counters#budNlr]]: N-bit binary up-down counter with syncronous load and asynchronous reset
* [[.:counters#guNar]]: N-bit gray up counter with asynchronous reset
* [[.:counters#gdNsr]]: N-bit gray down counter with synchronous reset
* [[.:counters#gudNlr]]: N-bit gray up-down counter with syncronous load and asynchronous reset
The COUNTERs library can be verified with this testbench: [[.:counters#testbench|test_counters]]
===== buNar =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : buNar : N-bit binary up counter #
-- # with asynchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
-- buNar Entity Description
entity buNar is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,R,UP: in std_ulogic;
COUT: out std_ulogic
);
end buNar;
-- buNar Architecture Description
architecture rtl of buNar is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
begin
count <= ('0' & istate) + "01";
Count_Process: process(CLK,R)
begin
if (R = '1') then
-- reset event
istate <= (OTHERS => '0');
elsif (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (UP = '1') then
-- clocked count up event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;
-- Assign output values
DOUT <= istate;
COUT <= count(N) and UP;
end rtl;
===== bdNsr =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : bdNsr : N-bit binary down counter #
-- # with synchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
-- bdNsr Entity Description
entity bdNsr is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,R: in std_ulogic;
COUT: out std_ulogic
);
end bdNsr;
-- bdNsr Architecture Description
architecture rtl of bdNsr is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
begin
count <= ('0' & istate) - "01";
Count_Process: process(CLK)
begin
if (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (R = '1') then
istate <= (OTHERS => '0');
elsif (DOWN = '1') then
-- clocked count down event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;
-- Assign output values
DOUT <= istate;
COUT <= '1' when (DOWN = '0') else not count(N);
end rtl;
===== budNlr =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : budNlr : N-bit binary up/down counter #
-- # with synchronous load and asynchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
-- budNlr Entity Description
entity budNlr is
generic(N: INTEGER := 8);
port(
DIN: in unsigned(N-1 downto 0);
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,LOAD,R,UP: in std_ulogic;
COUT: out std_ulogic
);
end budNlr;
-- budNlr Architecture Description
architecture rtl of budNlr is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
begin
count <= ('0' & istate) + "01" when ((UP = '1') and (DOWN = '0')) else
('0' & istate) - "01" when ((DOWN = '1') and (UP = '0')) else
('0' & istate);
Count_Process: process(CLK,R)
begin
if (R = '1') then
-- reset event
istate <= (OTHERS => '0');
elsif (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (LOAD = '1') then
-- clocked load event
istate <= DIN;
elsif (UP = '1') or (DOWN = '1') then
-- clocked count up/down event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;
-- Assign output values
DOUT <= istate;
COUT <= '0' when (DOWN = '0' and UP = '0')
else '1' when (DOWN = '1' and UP = '1')
else not count(N) when (DOWN = '1' and UP = '0')
else count(N);
end rtl;
===== guNar =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : guNar : N-bit gray up counter #
-- # with asynchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
use work.useful_functions.ALL;
-- guNar Entity Description
entity guNar is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,R,UP: in std_ulogic;
COUT: out std_ulogic
);
end guNar;
-- guNar Architecture Description
architecture rtl of guNar is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
signal binary_out : unsigned(N downto 0);
begin
count <= ('0' & istate) + "01";
Count_Process: process(CLK,R)
begin
if (R = '1') then
-- reset event
istate <= (OTHERS => '0');
elsif (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (UP = '1') then
-- clocked count up event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;
-- Convert input to binary representation
Bin2Grey(istate,binary_out);
-- Assign output values
DOUT <= binary_out(N-1 downto 0);
COUT <= count(N) and UP;
end rtl;
===== gdNsr =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : gdNsr : N-bit gray down counter #
-- # with synchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
use work.useful_functions.ALL;
-- gdNsr Entity Description
entity gdNsr is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,R: in std_ulogic;
COUT: out std_ulogic
);
end gdNsr;
-- gdNsr Architecture Description
architecture rtl of gdNsr is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
signal binary_out : unsigned(N downto 0);
begin
count <= ('0' & istate) - "01";
Count_Process: process(CLK)
begin
if (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (R = '1') then
istate <= (OTHERS => '0');
elsif (DOWN = '1') then
-- clocked count down event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;
-- Convert input to binary representation
Bin2Grey(istate,binary_out);
-- Assign output values
DOUT <= binary_out(N-1 downto 0);
COUT <= '1' when (DOWN = '0') else not count(N);
end rtl;
===== gudNlr =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : counters.vhd #
-- # #
-- # Component : gudNlr : N-bit gray up/down counter #
-- # with synchronous load and asynchronous reset #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.ALL;
use work.useful_functions.ALL;
-- gudNlr Entity Description
entity gudNlr is
generic(N: INTEGER := 8);
port(
DIN: in unsigned(N-1 downto 0);
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,LOAD,R,UP: in std_ulogic;
COUT: out std_ulogic
);
end gudNlr;
-- gudNlr Architecture Description
architecture rtl of gudNlr is
signal istate : unsigned(N-1 downto 0);
signal count : unsigned(N downto 0);
signal load_value : unsigned(N-1 downto 0);
signal binary_out : unsigned(N downto 0);
begin
-- Convert input to binary representation
Grey2Bin(DIN,load_value);
count <= ('0' & istate) + "01" when ((UP = '1') and (DOWN = '0')) else
('0' & istate) - "01" when ((DOWN = '1') and (UP = '0')) else
('0' & istate);
Count_Process: process(CLK,R)
begin
if (R = '1') then
-- reset event
istate <= (OTHERS => '0');
elsif (CLK'event and (CLK = '1') and (CLK'last_value = '0')) then
if (LOAD = '1') then
-- clocked load event
istate <= load_value;
elsif (UP = '1') or (DOWN = '1') then
-- clocked count up/down event
istate <= count(N-1 downto 0);
end if;
end if;
end process Count_Process;
-- Convert input to binary representation
Bin2Grey(istate,binary_out);
-- Assign output values
DOUT <= binary_out(N-1 downto 0);
COUT <= '0' when (DOWN = '0' and UP = '0')
else '1' when (DOWN = '1' and UP = '1')
else not count(N) when (DOWN = '1' and UP = '0')
else count(N);
end rtl;
===== Testbench =====
-- ############################################################################
-- # Project : Leonardo CBT-Kernel #
-- # #
-- # Filename : test_counters.vhd #
-- # #
-- # Component : test_counters : Test Bench for various counters. #
-- # #
-- # Model : rtl #
-- # #
-- # Designer : S. Theoharis,N. Zervas #
-- # Institute : VLSI Design Lab., University of Patras #
-- # Date : 01.05.1999 #
-- ############################################################################
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity test_counters IS
END test_counters;
ARCHITECTURE rtl OF test_counters IS
COMPONENT bdNsr is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,R: in std_ulogic;
COUT: out std_ulogic
);
end COMPONENT;
COMPONENT buNar is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,R,UP: in std_ulogic;
COUT: out std_ulogic
);
end COMPONENT;
COMPONENT budNlr is
generic(N: INTEGER := 8);
port(
DIN: in unsigned(N-1 downto 0);
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,LOAD,R,UP: in std_ulogic;
COUT: out std_ulogic
);
END COMPONENT;
COMPONENT gdNsr is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,R: in std_ulogic;
COUT: out std_ulogic
);
END COMPONENT;
COMPONENT guNar is
generic(N: INTEGER := 4);
port(
DOUT: out unsigned(N-1 downto 0);
CLK,R,UP: in std_ulogic;
COUT: out std_ulogic
);
END COMPONENT;
COMPONENT gudNlr is
generic(N: INTEGER := 8);
port(
DIN: in unsigned(N-1 downto 0);
DOUT: out unsigned(N-1 downto 0);
CLK,DOWN,LOAD,R,UP: in std_ulogic;
COUT: out std_ulogic
);
END COMPONENT;
FOR ALL : bdNsr USE ENTITY WORK.bdNsr(rtl);
FOR ALL : buNar USE ENTITY WORK.buNar(rtl);
FOR ALL : budNlr USE ENTITY WORK.budNlr(rtl);
FOR ALL : gdNsr USE ENTITY WORK.gdNsr(rtl);
FOR ALL : guNar USE ENTITY WORK.guNar(rtl);
FOR ALL : gudNlr USE ENTITY WORK.gudNlr(rtl);
CONSTANT N : integer := 8;
SIGNAL DIN3,DIN6,DOUT1,DOUT2,DOUT3,DOUT4,DOUT5,DOUT6 : unsigned(N-1 downto 0);
SIGNAL RESET,CLK,LOAD,UP,DOWN : std_ulogic := '0';
SIGNAL COUT1,COUT2,COUT3,COUT4,COUT5,COUT6 : std_ulogic;
BEGIN
Binary_down_counter : bdNsr
GENERIC MAP (
N=>N
)
PORT MAP (
DOUT=>DOUT1,
CLK=>CLK,
DOWN=>DOWN,
R=>RESET,
COUT=>COUT1
);
Binary_up_counter : buNar
GENERIC MAP (
N=>N
)
PORT MAP (
DOUT=>DOUT2,
CLK=>CLK,
UP=>UP,
R=>RESET,
COUT=>COUT2
);
Binary_up_down_counter : budNlr
GENERIC MAP (
N=>N
)
PORT MAP (
DIN=>DIN3,
DOUT=>DOUT3,
CLK=>CLK,
DOWN=>DOWN,
UP=>UP,
LOAD=>LOAD,
R=>RESET,
COUT=>COUT3
);
Gray_down_counter : gdNsr
GENERIC MAP (
N=>N
)
PORT MAP (
DOUT=>DOUT4,
CLK=>CLK,
DOWN=>DOWN,
R=>RESET,
COUT=>COUT4
);
Gray_up_counter : guNar
GENERIC MAP (
N=>N
)
PORT MAP (
DOUT=>DOUT5,
CLK=>CLK,
UP=>UP,
R=>RESET,
COUT=>COUT5
);
Gray_up_down_counter : gudNlr
GENERIC MAP (
N=>N
)
PORT MAP (
DIN=>DIN6,
DOUT=>DOUT6,
CLK=>CLK,
DOWN=>DOWN,
UP=>UP,
LOAD=>LOAD,
R=>RESET,
COUT=>COUT6
);
DIN3 <= "00000100";
DIN6 <= "00001100";
CLK <= not CLK AFTER 50 ns;
RESET <= '1', '0' AFTER 120 ns;
LOAD <= '0', '1' AFTER 1000 ns, '0' AFTER 1100 ns;
UP <= '0', '1' AFTER 2000 ns;
DOWN <= '1', '0' AFTER 2000 ns;
END rtl;