====== Synthesis ======
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  * [[.:RTL-Style]]
  * [[.:What is Synthesis]]
  * Finite State Machines and VHDL
    * [[.:Finite State Machines and VHDL:start|Introduction]]
    * [[.:Finite State Machines and VHDL:State Processes]]
    * [[.:Finite State Machines and VHDL:State Coding]]
    * [[.:Finite State Machines and VHDL:Medvedev]]
    * [[.:Finite State Machines and VHDL:Moore]]
    * [[.:Finite State Machines and VHDL:Mealy]]
    * [[.:Finite State Machines and VHDL:Registered Output]]
    * [[.:Finite State Machines and VHDL:FSM and Simulation]]
    * [[.:Finite State Machines and VHDL:FSM and Synthesis]]
  * Combinational Logic
    * [[.:Combinational Logic:start|Combinational Logic]]
    * [[.:Combinational Logic:Example of a Multiplier]]
    * [[.:Combinational Logic:Differences in Synthesis]]
  * [[.:Sequential Logic]]
  * [[.:Advanced Synthesis]]
  * [[.:Controlling Synthesis]]
  * Master-Slave Flip-Flop
    * [[.:Master-Slave Flip-Flop:start|Why MSFF?]]
    * [[.:Master-Slave Flip-Flop:RS-FF]]
    * [[.:Master-Slave Flip-Flop:D-FF]]
    * [[.:Master-Slave Flip-Flop:JK-FF]]
    * [[.:Master-Slave Flip-Flop:Toggle-FF]]
    * [[.:Master-Slave Flip-Flop:Multifunctional-FF]]
    * [[.:Master-Slave Flip-Flop:Timing behavior]]
  * [[.:Quiz]]
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