====== RTL-Style ======
after "Process Types":

===== Combinatorics =====
<code vhdl>
Library IEEE;
use IEEE.Std_Logic_1164.all;
   
entity IF_EXAMPLE is
port (A, B, C, X : in std_ulogic_vector(3 downto 0);
          Z                : out std_ulogic_vector(3 downto 0));
end IF_EXAMPLE;
   
architecture A of IF_EXAMPLE is
begin
     process (A, B, C, X)
     begin
        if ( X = "1110" ) then
           Z <= A;
        elsif (X = "0101") then
           Z <= B;
        else
           Z <= C;
        end if;
     end process;
end A;
</code>

{{:courses:system_design:synthesis:lost_combinatorics.svg?nolink&250|Combinatorics}}

<callout>
=== Notes ===
An IF assignment is always implemented as one or several mutliplexers in the synthesis. With it, every condition corresponds to a multiplexer (IF or ELSIF branch).
Please note the priority of the single branches. In the simulation of an IF assignment, when entering a condition, the others following will not be worked off.
This branches' order must be kept in the synthesis, as well. Yet, it is only possible by means of series connected multiplexers, whereas the FIRST condition is attached to the SELECT entry of the LAST multiplexer.
</callout>

===== Modelling of Flip Flops =====
<code vhdl>
Library IEEE;
use IEEE.Std_Logic_1164.all;
  
entity FLOP is
port (D, CLK        : in std_ulogic;
         Q                  : out std_ulogic);
end FLOP;
  
architecture A of FLOP is
begin
      process
      begin
          wait until CLK`event and CLK=`1`;
          Q <= D;
      end process;
end A;
</code>

<callout>
=== Notes ===
Here, a D-flip-flop controlled by a clock pulse edge is described. If an event occurs at the clock signal and this event has the value ONE, the value of the pin D will be transferred to the pin Q.
(You could also await the negative clock pulse edge, then must be: CLK='0').
</callout>

====== Combinational Logic ======
after "Synthesis of Operators":

===== Synthesis Results =====
  * Step 1: Conversion into a generic netlist
    * VHDL -> either boolean equations (more or less complicated) or the tool recognizes a complex function
  * Step 2: Optimization
  * Depends on the tool: all three examples provide the same result

{{:courses:system_design:synthesis:lost_synthesisresultmultiplier.svg?nolink&150|Synthesis Result Multiplier}}

===== Example of an Adder =====
<code vhdl>
entity ADD is
   port (A, B  : in integer range 0 to 7;
           Z   : out integer range 0 to 15);
end ADD;

architecture ARITHMETIC of ADD is
begin
    Z <= A + B;
end ARITHMETIC;
</code>

Notice: Advantages of a range declaration with integer types:
    - During simulation: check for "out of range..."
    - During synthesis: only 4 bit bus width

Package with "+" functions
<code vhdl>
library VENDOR_XY;
use VENDOR_XY.p_arithmetic.all;

entity MVL_ADD is
   port (A, B : in mvl_vector (3 downto 0);
            Z : out mvl_vector (4 downto 0) );
end MVL_ADD;

architecture ARITHMETIC of MVL_ADD is
begin
    Z <= A + B;
end ARITHMETIC;
</code>

{{:courses:system_design:synthesis:lost_synthesisresultadder.svg?nolink&150|Example of an Adder}}

<callout>
=== Notes ===
You could follow the same steps shown above with the multiplier when implementing an adder. But as we already know the smartest way of coding an adder in VHDL is to use integer types and the operator '+'. The number of bits per port signal is determined by the range constraint. The operator "+" can be transferred into the function table and into boolean expressions, i.e. gates, by a synthesis tool.

It is more complicated when using self defined data types (non integer). The VHDL standard as stated in the LRM (Language Reference Manual) predefines such arithmetic operators only for INTEGER and REAL data types. Therefore it is necessary to describe a new "+" operator in VHDL.

This new function (with the same name "+", but with new parameters) might look like:

          function "+"(L: mvl_vector; R: mvl_vector) return mvl_vector is
          constant length: INTEGER := R'length + 1;
          begin
               -- calculate result = L + R
              return result;
          end;
</callout>

====== Sequential Logic ======
===== Example =====
<code vhdl>
process
   variable LFSR : bit_vector(3 downto 0);
begin
   wait until CLK`event and CLK=`1`;
      LFSR(0) := INPUT;
      LFSR(3) := LFSR(2);
      LFSR(2) := LFSR(1);
      LFSR(1) := LFSR(0);
  
      OUTPUT <= LFSR(3);
end process;
</code>

How many registers are generated?

<callout>
=== Notes ===
Three FlipFlop will be implemented. One for the signal OUTPUT, which is driven within the clocked process. Two FlipFlops will be implemented for the variables LFSR(2) and LFSR(1), as they are read before they are driven.
</callout>