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**Chapters of System Design > Synthesis > Finite State Machines and VHDL**
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  * [[.:start|Introduction]]
  * [[.:State Processes]]
  * [[.:State Coding]]
  * [[.:Medvedev]]
  * [[.:Moore]]
  * [[.:Mealy]]
  * [[.:Registered Output]]
  * [[.:FSM and Simulation]]
  * [[.:FSM and Synthesis]]
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