library ieee;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;

entity DISP_CTRL is
  -- system signals: CLK, RESET
  -- control signals: SWITCH, KEY
  -- output signal: SHOW_TIME
end DISP_CTRL;

architecture RTL of DISP_CTRL is
  -- Internal signal for SHOW_TIME output
begin
  -- Output assignment
  -- Clocked process with asynchronous reset
  process
    variable LAST_SWITCH: std_ulogic;
  begin
    if (RESET = '1') then
      -- Reset all registers
    elsif (CLK'event and CLK = '1') then
      if KEY /= (0,0,0) then
        SHOW_STATE <= '1';
      else
        if LAST_SWITCH = '0' and SWITCH = '1' then
          -- Toggle output signal
        end if;
      end if;
      
      -- Store the SWITCH value to allow a rising edge detection
      LAST_SWITCH := SWITCH;
    end if; -- end of clocked process
  end process;
end RTL;