library ieee;
use ieee.std_logic_1164.all;
use work.P_DISPLAY.all;

entity TB_DECODER is
end TB_DECODER;

architecture TEST of TB_DECODER is
  component DECODER
    port (KEYPAD : in std_ulogic_vector (9 downto 0);
          KEY    : out T_DIGITS);
  end component;
  
  signal W_KEYPAD : std_ulogic_vector (9 downto 0);
  signal W_KEY : T_DIGITS;

begin
  DUT : DECODER
    port map (KEYPAD => W_KEYPAD,
              KEY    => W_KEY);

  STIMULI : process
  begin
    W_KEYPAD <= "1000000000";
    -- KEY = (5,1,2) (this works in both architectures!!)
    wait for 20 ns;
    
    W_KEYPAD <= "1111100000";
    -- KEY = (0,3,2) (if)
    --       (0,0,0) (case)
    wait for 20 ns;
    
    W_KEYPAD <= "0000100000";
    -- KEY = (0,3,2) (both architectures)
    wait for 20 ns;
    
    for I in 9 downto 0 loop
      W_KEYPAD <= (others => '0');
      W_KEYPAD(I) <= '1';
      -- KEY = (5,1,2),(2,5,6),(1,2,8),(0,6,4),(0,3,2),
      --       (0,1,6),(0,0,8),(0,0,4),(0,0,2),(0,0,1)
      --       (both architectures)
      wait for 20 ns;
    end loop;
    wait;
  end process STIMULI;
end TEST;

configuration CFG_TB_DECODER of TB_DECODER is
  for TEST
  end for;
end CFG_TB_DECODER;