-- ############################################################################
-- # Project    :    VHDL-Modellbibliothek				      #
-- #                                                                          #
-- # Filename   :    tb_lin_sync_counter.vhd                                  #
-- #                                                                          #
-- # Schaltung  :    Testbench fuer synchronen Auf-/Abwaertszaehler mit       # 
-- #		     ladbarem Zaehlerinhalt                                   #
-- #                                                                          #
-- #                 tb_lin_sync_counter     	                              #
-- #                                                                          #
-- # Designer   : Wolfgang Sehr; ueberarbeitet von Stefan Schmechtig          #
-- # Abteilung  : Lehrstul fuer rechnergestuetzten Schaltungsentwurf          #
-- # Datum      : 23.02.1995                                                  #
-- ############################################################################

-- ############################################################################
-- #                        IEEE - PACKAGES                                   #
-- ############################################################################
   Library IEEE;
   use IEEE.std_logic_1164.all;
   use IEEE.std_logic_arith.all;
   USE IEEE.math_real.all; 	-- wird fuer die Erzeugung von Zufallszahlen
				-- benoetigt 
-- ############################################################################


ENTITY TB_lin_sync_counter IS
	GENERIC (BITBR: INTEGER := @BITBR);  -- Bitbr: Bitbreite des Zaehlers
END TB_lin_sync_counter;


ARCHITECTURE behaviour of TB_lin_sync_counter IS
SIGNAL	tb_takt			: STD_LOGIC;
SIGNAL	tb_reset		: STD_LOGIC;
SIGNAL	tb_mode			: STD_LOGIC;
SIGNAL	tb_zaehl		: STD_LOGIC;
SIGNAL	tb_laden		: STD_LOGIC;
SIGNAL	tb_null_detect		: STD_LOGIC;
SIGNAL	tb_zaehl_start_wert	: UNSIGNED((BITBR-1) DOWNTO 0);

COMPONENT lin_sync_counter
	PORT	(takt			: IN STD_LOGIC;
	  	 reset			: IN STD_LOGIC;
		 mode			: IN STD_LOGIC;
		 zaehl			: IN STD_LOGIC;
		 laden			: IN STD_LOGIC;
		 null_detect		: OUT STD_LOGIC;
		 zaehl_start_wert	: IN UNSIGNED((BITBR-1) DOWNTO 0)
		);
END COMPONENT;

BEGIN
   UUT: lin_sync_counter
	PORT MAP (	takt			=> tb_takt,
	  	 	reset			=> tb_reset,
		 	mode			=> tb_mode,
		 	zaehl			=> tb_zaehl,
		 	laden			=> tb_laden,
		 	null_detect		=> tb_null_detect,
		 	zaehl_start_wert	=> tb_zaehl_start_wert
		);
stim_1: PROCESS
    	BEGIN
	   tb_takt <= '1';
	   WAIT FOR 10 ns;

	   LOOP
	       tb_takt <= NOT (tb_takt);
	       WAIT FOR 10 ns;
	   END LOOP;
	END PROCESS;

stim_2: PROCESS
	BEGIN
	   tb_reset <= '1';
	   WAIT FOR 15 ns;

	   LOOP
	      tb_reset <= NOT (tb_reset);
	      WAIT FOR 200 ns;
	      
	      tb_reset <= NOT (tb_reset);
	      WAIT FOR 200 ns;
	   END LOOP;
	END PROCESS;

stim_3: PROCESS
	BEGIN
	   tb_mode <= '1';
	   WAIT FOR 100 ns;
	
	   LOOP
	     tb_mode <= NOT(tb_mode);
	     WAIT FOR 100 ns;
	   END LOOP;
	END PROCESS;

stim_4: PROCESS
	BEGIN 
	   tb_zaehl <= '1';
	   WAIT FOR 30 ns;
	   
 	   LOOP
	      tb_zaehl <= NOT (tb_zaehl);
	      WAIT FOR 20 ns;
	   END LOOP;
	END PROCESS;

stim_5: PROCESS
	BEGIN
	    tb_laden <= '0';
	    WAIT FOR 70 ns;

	    LOOP
	       tb_laden <= NOT (tb_laden);
	       WAIT FOR 20 ns;

	       tb_laden <= NOT (tb_laden);
	       WAIT FOR 70 ns;
	    END LOOP; 
	END PROCESS;

stim_6: PROCESS
	BEGIN
	    LOOP
	       tb_zaehl_start_wert <= CONV_UNSIGNED(RAND, 
						    tb_zaehl_start_wert'LENGTH);
		WAIT FOR 30 ns;
	    END LOOP;
	END PROCESS;

END behaviour;


CONFIGURATION CFG_TB_lin_sync_counter OF TB_lin_sync_counter IS
   FOR behaviour
	FOR UUT: lin_sync_counter
	   USE CONFIGURATION WORK.CFG_lin_sync_counter;
	END FOR;
   END FOR;
END CFG_TB_lin_sync_counter;