-- ###############################################################################
-- # Project    :    Leonardo CBT-Kernel                                         #
-- #                                                                             #
-- # Filename   :    test_universal_multiplier.vhd                               #
-- #                                                                             #
-- # Component  : test_univ_multiplier : Test bench for Universal multiplier of  #
-- #                                     NxM bits.                               #
-- #              According to MODE operand one of the following multiplications #
-- #              are performed :                                                #
-- #              MODE="00" : unsigned multiplication.                           #
-- #              MODE="01" : sign magnitude multiplication.                     #
-- #              MODE="10" : 1s complement multiplication.                      #
-- #              MODE="11" : 2s complement multiplication.                      #
-- #                                                                             #
-- #              GENERICS :                                                     #
-- #                     N : # of bits of X operand (multiplicand).              #
-- #                     M : # of bits of Y operand (multiplier).                #
-- #              For better synthesis results , M must be less or equal to N.   #
-- #                                                                             #
-- # Model      :    rtl                                                         #
-- #                                                                             #
-- # Designer   :    S. Theoharis                                                #
-- # Institute  :    VLSI Design Lab., University of Patras                      #
-- # Date       :    01.05.1999                                                  #
-- ###############################################################################

-------------------------
-- Library declaration --
-------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

------------------------
-- Entity declaration --
------------------------
ENTITY test_universal_multiplier IS
END test_universal_multiplier;

------------------------------
-- Architecture declaration --
------------------------------
ARCHITECTURE behav OF test_universal_multiplier IS

---------------------------
-- Component declaration --
---------------------------
COMPONENT universal_multiplier IS
GENERIC (
         N : integer:= 4; -- # bits of X opernand.
         M : integer:= 4  -- # bits of Y opernand.
        );
PORT (
      X    : IN  std_ulogic_vector(N-1 downto 0);
      Y    : IN  std_ulogic_vector(M-1 downto 0);
      MODE : IN  std_ulogic_vector(1 downto 0);
      Z    : OUT std_ulogic_vector(N+M-1 downto 0)
     );
END COMPONENT;

-- UNSIGNED="00" , SIGN_MAGNITUDE="01" , 1s COMPLEMENT="10" , 2s COMPLEMENT="11"
constant X_WIDTH  : integer := 4;
constant Y_WIDTH  : integer := 4;

------------------------
-- Signal declaration --
------------------------
SIGNAL X : std_ulogic_vector(X_WIDTH-1 downto 0) := (OTHERS=>'0');
SIGNAL Y : std_ulogic_vector(Y_WIDTH-1 downto 0) := (OTHERS=>'0');
SIGNAL MODE : std_ulogic_vector(1 downto 0);
SIGNAL Z : std_ulogic_vector(X_WIDTH+Y_WIDTH-1 downto 0) := (OTHERS=>'0');

SIGNAL X_int,Y_int,Z_int : integer := 0;
 
signal reset : std_ulogic := '1';
signal clk   : std_ulogic := '0';

BEGIN

-----------------------
-- Increment Process --
-----------------------
reset <= '1', '0' after 80 ns;

PROCESS(clk)
BEGIN
clk <= '1' xor clk after 50 ns;
END PROCESS;

PROCESS(clk,reset)
BEGIN
	IF (reset='1') THEN
		X_int <= 0;
		Y_int <= 0;
     	ELSIF (rising_edge(clk)) THEN
        	IF (Y_int=2**Y_WIDTH-1) THEN
			Y_int <= 0;
			X_int <= X_int + 1;
		ELSE
            	Y_int <= Y_int + 1;
        	END IF;
	END IF;
END PROCESS;

Z_int <= X_int * Y_int;

------------------------------
-- Component instantiation. --
------------------------------

X <= to_stdulogicvector(X_int,X_WIDTH);
Y <= to_stdulogicvector(Y_int,Y_WIDTH);

u1 : universal_multiplier 
     GENERIC MAP (
                  N=>X_WIDTH,
                  M=>Y_WIDTH
                 )
     PORT MAP (
               X=>X,
               Y=>Y,
               MODE=>MODE,
               Z=>Z);

MODE <= "01";

--------------------
-- Check results. --
--------------------
PROCESS(clk)
BEGIN
	IF (rising_edge(clk)) THEN
      -- Unsigned multiplication.
      IF (MODE="00") THEN
	      ASSERT (Z=to_stdulogicvector(Z_int,X_WIDTH+Y_WIDTH))
      		REPORT "Error in multiplication!"
       	SEVERITY FAILURE;
      END IF;

      -- Check if X,Y have taken all the values.
	ASSERT (X_int/=2**X_WIDTH-1 OR Y_int/=2**Y_WIDTH-1)
       	REPORT "Simulation is finished succesfully!"
      SEVERITY FAILURE;
END IF;
END PROCESS;

END behav;