-- ###############################################################################
-- # Project    :    Leonardo CBT-Kernel                                         #
-- #                                                                             #
-- # Filename   :    universal_multiplier.vhd                                    #
-- #                                                                             #
-- # Component  : universal_multiplier : Universal multiplier NxM bits.          #
-- #              According to MODE operand one of the following multiplications #
-- #              are performed :                                                #
-- #              MODE="00" : unsigned multiplication.                           #
-- #              MODE="01" : sign magnitude multiplication.                     #
-- #              MODE="10" : 1s complement multiplication.                      #
-- #              MODE="11" : 2s complement multiplication.                      #
-- #                                                                             #
-- #              GENERICS :                                                     #
-- #                     N : # of bits of X operand (multiplicand).              #
-- #                     M : # of bits of Y operand (multiplier).                #
-- #              For better synthesis results , M must be less or equal to N.   #
-- #                                                                             #
-- # Model      :    rtl                                                         #
-- #                                                                             #
-- # Designer   :    S. Theoharis                                                #
-- # Institute  :    VLSI Design Lab., University of Patras                      #
-- # Date       :    01.05.1999                                                  #
-- ###############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

ENTITY universal_multiplier IS
GENERIC (
         N : integer:= 4; -- # bits of X opernand.
         M : integer:= 4  -- # bits of Y opernand.
        );
PORT (
      X    : IN  std_ulogic_vector(N-1 downto 0);
      Y    : IN  std_ulogic_vector(M-1 downto 0);
      MODE : IN  std_ulogic_vector(1 downto 0);
      Z    : OUT std_ulogic_vector(N+M-1 downto 0)
     );
END universal_multiplier;

ARCHITECTURE behav OF universal_multiplier IS
SIGNAL X_un : unsigned(N-1 downto 0);
SIGNAL Y_un : unsigned(M-1 downto 0);
SIGNAL Z_un : unsigned(N+M-1 downto 0);
BEGIN

X_un <= conv_unsigned(conv_integer("0" & X),N);
Y_un <= conv_unsigned(conv_integer("0" & Y),M);

Multiplier : PROCESS(MODE,X_un,Y_un)
VARIABLE t_X : unsigned(N-1 downto 0);
VARIABLE t_Y : unsigned(M-1 downto 0);
VARIABLE t_Z : unsigned(N+M-1 downto 0);
VARIABLE sign_X,sign_Y,sign_Z : std_logic;
BEGIN
IF (MODE="00") THEN                 -- Unsigned multiplication.
             Z_un <= X_un * Y_un;
ELSIF (MODE="01") THEN              -- Sign magnitude multiplication.
	       Z_un(N+M-3 downto 0) <= X_un(N-2 downto 0) * Y_un(M-2 downto 0);
             Z_un(N+M-2) <= '0';
             Z_un(N+M-1) <= X_un(N-1) xor Y_un(M-1);
ELSIF (MODE="10" or MODE="11") THEN -- 1s/2s complement multiplication.
             t_X := X_un;
             t_Y := Y_un;
             sign_X := X_un(N-1);
             sign_Y := Y_un(M-1);
             sign_Z := sign_X xor sign_Y;
             IF (sign_X='1') THEN
			t_X(N-2 downto 0) := not t_X(N-2 downto 0);
                  IF (MODE="11") THEN
				t_X(N-2 downto 0) := t_X(N-2 downto 0) + "1";
 		 	END IF;
             END IF;
             IF (sign_Y='1') THEN
			t_Y(M-2 downto 0) := not t_Y(M-2 downto 0);
                  IF (MODE="11") THEN
				t_Y(M-2 downto 0) := t_Y(M-2 downto 0) + "1";
 		 	END IF;
             END IF;
	       t_Z(N+M-3 downto 0) := t_X(N-2 downto 0) * t_Y(M-2 downto 0);
             IF (sign_Z='1') THEN
			t_Z(N+M-3 downto 0) := not t_Z(N+M-3 downto 0);
                  IF (MODE="11") THEN
				t_Z(M+N-3 downto 0) := t_Z(N+M-3 downto 0) + "1";
 		 	END IF;
             END IF;
             t_Z(N+M-2) := sign_Z;
             t_Z(N+M-1) := sign_Z;
             Z_un <= t_Z;
END IF;       
END PROCESS Multiplier;

Z <= to_stdulogicvector(conv_integer(Z_un),N+M);

END behav;