-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    test_increments_decrements.vhd                           #
-- #                                                                          #
-- # Component  :    test_increments_decrements : Test Bench for various      #
-- #                                              incrementers/decrementers.  #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity test_increments_decrements IS
END test_increments_decrements;

ARCHITECTURE rtl OF test_increments_decrements IS

COMPONENT decrN is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      D: out unsigned(N-1 downto 0);
      DN: in std_ulogic;
      COUT,ZERO: out std_ulogic
   );
end COMPONENT;

COMPONENT incN is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      D: out unsigned(N-1 downto 0);
      UP: in std_ulogic;
      COUT,ZERO: out std_ulogic
   );
end COMPONENT;

COMPONENT incdecN is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      D: out unsigned(N-1 downto 0);
      DN,UP: in std_ulogic;
      COUT,ZERO: out std_ulogic
   );
END COMPONENT;

 FOR ALL : incN USE ENTITY WORK.incN(rtl);
 FOR ALL : decrN USE ENTITY WORK.decrN(rtl);
 FOR ALL : incdecN USE ENTITY WORK.incdecN(rtl);
 
 CONSTANT N : integer := 4;
 SIGNAL A1,A2,A3,D1,D2,D3 : unsigned(N-1 downto 0) := (OTHERS=>'0');
 SIGNAL COUT1,ZERO1,COUT2,ZERO2,COUT3,ZERO3 : std_ulogic;
 SIGNAL UP : std_ulogic := '0';
 SIGNAL DOWN : std_ulogic := '1';
 
 BEGIN

Decrementer : decrN
           GENERIC MAP (
                        N=>N
                       )
           PORT MAP (
                     A=>A1,
                     D=>D1,
                     DN=>DOWN,
                     COUT=>COUT1,
                     ZERO=>ZERO1
                    );

Incrementer : incN
           GENERIC MAP (
                        N=>N
                       )
           PORT MAP (
                     A=>A2,
                     D=>D2,
                     UP=>UP,
                     COUT=>COUT2,
                     ZERO=>ZERO2
                    );

Incrementer_Decrementer : incdecN
           GENERIC MAP (
                        N=>N
                       )
           PORT MAP (
                     A=>A3,
                     D=>D3,
                     DN=>DOWN,
                     UP=>UP,
                     COUT=>COUT3,
                     ZERO=>ZERO3
                    );

A1 <= "0001";
A2 <= "0010";
A3 <= "0011";

UP <= not UP AFTER 50 ns;
DOWN <= not DOWN AFTER 50 ns; 

END rtl;