-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    increments_decrements.vhd                                #
-- #                                                                          #
-- # Component  :    decrN : N-bit decrementer                                #
-- #                                                                          #
-- # Model      :    rtl                                                      #
-- #                                                                          #
-- # Designer   :    S. Theoharis,N. Zervas                                   #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use work.useful_functions.all;

-- decrN Entity Description
entity decrN is
   generic(N: INTEGER := 4);
   port(
      A: in unsigned(N-1 downto 0);
      D: out unsigned(N-1 downto 0);
      DN: in std_ulogic;
      COUT,ZERO: out std_ulogic
   );
end decrN;

-- decrN Architecture Description
architecture rtl of decrN is
   signal extended : unsigned(N downto 0);
begin
   DECREMENTER_Process: process(A,DN) begin
      if (DN = '1') then
         extended <= ('0' & A) - "01";
      else
         extended <= ('0' & A);
      end if;
   end process DECREMENTER_Process;
 
   -- Assign output values
   D <= extended(N-1 downto 0);
   COUT <= extended(N);
   ZERO <= '1' when vector_eq_zero(extended(N-1 downto 0)) else '0';
end rtl;