-- ############################################################################ -- # Project : Leonardo CBT-Kernel # -- # # -- # Filename : test_fir.vhd # -- # # -- # Component : test_fir : Test bench for an FIR of N_taps-Wx x Wc Bits. # -- # # -- # Model : behav # -- # # -- # Designer : S. Theoharis # -- # Institute : VLSI Design Lab., University of Patras # -- # Date : 01.05.1999 # -- ############################################################################ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; USE std.TEXTIO.ALL; USE work.fir_lib.ALL; ENTITY test_fir IS END test_fir; ARCHITECTURE behav OF test_fir IS -------------------------------------------------------------- COMPONENT fir GENERIC ( N_taps : integer := 4; -- # shifter's words. Wx : integer := 6 -- # bits/sample. ); PORT ( X : IN std_ulogic_vector(Wx-1 downto 0); C : IN fir_coefficient_type; CLK : IN std_ulogic; RESETB : IN std_ulogic; Y : OUT std_ulogic_vector(Wx-1 downto 0) ); END COMPONENT; -------------------------------------------------------------- TYPE sample_values IS FILE OF CHARACTER; FILE file_in : sample_values IS IN "./lena256.raw"; FILE file_out : sample_values IS OUT "./lena256_fir.raw"; -- FILE file_in : sample_values IS "./lena256.raw"; -- FILE file_out : sample_values IS "./lena256_fir.raw"; SIGNAL CLK,RESETB : std_ulogic := '0'; SIGNAL X,Y : std_ulogic_vector(Wx-1 downto 0); SIGNAL FIR_Coefficients : fir_coefficient_type; CONSTANT BINARY_VALUES : boolean := FALSE; SIGNAL X_int,Y_int : integer RANGE 0 TO 2**Wx-1; BEGIN -------------------------------------------------------------- X_int <= conv_integer('0' & X); Y_int <= conv_integer('0' & Y); FIR_coefficients <= C_matrix; RESETB <= '0', '1' AFTER 20 ns; CLK <= '1' xor CLK AFTER 50 ns; -------------------------- -- X sample generation. -- -------------------------- PROCESS(RESETB,CLK) VARIABLE char : CHARACTER; VARIABLE tmp_X : integer; BEGIN -- (1) Create binary counter values ... IF (BINARY_VALUES) THEN IF (RESETB='0') THEN X <= (OTHERS=>'0'); ELSIF (rising_edge(CLK)) THEN tmp_X := conv_integer('0' & X); IF (tmp_X=2**Wx-1) THEN tmp_X := 0; ELSE tmp_X := tmp_X + 1; END IF; X <= to_stdulogicvector(tmp_X,Wx); END IF; ELSE -- (2) Read values from file ... IF (RESETB='0') THEN X <= (OTHERS=>'0'); ELSIF (rising_edge(CLK)) THEN IF (NOT ENDFILE(file_in)) THEN READ(file_in,char); X <= to_stdulogicvector(CHARACTER'pos(char),Wx); END IF; ASSERT (NOT ENDFILE(file_in)) REPORT "End of file ./do/lena256.raw" SEVERITY FAILURE; END IF; END IF; END PROCESS; -------------------------------------------------------------- FIR_inst : fir GENERIC MAP ( N_taps=>N_taps, Wx=>Wx ) PORT MAP ( X=>X, C=>FIR_coefficients, CLK=>CLK, RESETB=>RESETB, Y=>Y ); -------------------------------------------------------------- END behav;