-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    in_shifter_fir.vhd                                       #
-- #                                                                          #
-- # Component  :    in_shifter_fir : N_taps-Wx Bit shifter                   #
-- #                                                                          #
-- # Model      :    behav                                                    #
-- #                                                                          #
-- # Designer   :    S. Theoharis                                             #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
USE work.fir_lib.ALL;

ENTITY in_shifter_fir IS
GENERIC (
	N_taps : integer := 4;  -- # shifter's words.
	Wx     : integer := 6   -- # bits/sample.
         ); 
PORT  (
       SI             : IN  std_ulogic_vector(Wx-1 downto 0);
	 CLK_SHIFT      : IN  std_ulogic;
	 RESETB         : IN  std_ulogic;
	 SO             : OUT fir_shifter_type
	);
END in_shifter_fir;

ARCHITECTURE behav OF in_shifter_fir IS
SIGNAL shifter : fir_shifter_type;
BEGIN

-- Shifter process : shifts out N samples of W bits.
Shifter_process : PROCESS(CLK_SHIFT,RESETB)
BEGIN
IF (RESETB='0') THEN
	FOR i IN N_taps-1 downto 0 LOOP
		shifter(i) <= (OTHERS=>'0');
	END LOOP;
ELSIF (rising_edge(CLK_SHIFT)) THEN
	shifter(N_taps-1 downto 0) <= shifter(N_taps-2 downto 0) & SI;
END IF;
END PROCESS Shifter_process;

SO <= shifter;

END behav;