-- ############################################################################
-- # Project    :    Leonardo CBT-Kernel                                      #
-- #                                                                          #
-- # Filename   :    fir.vhd                                                  #
-- #                                                                          #
-- # Component  :    fir : N_taps-Wx x Wc Bits FIR (unrolled)                 #
-- #                                                                          #
-- # Model      :    behav                                                    #
-- #                                                                          #
-- # Designer   :    S. Theoharis                                             #
-- # Institute  :    VLSI Design Lab., University of Patras                   #
-- # Date       :    01.05.1999                                               #
-- ############################################################################

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
USE work.fir_lib.ALL;

ENTITY fir IS
GENERIC (
	   N_taps : integer := 4;  -- # FIR's taps.
	   Wx     : integer := 4;  -- # bits/X sample.
	   Wc     : integer := 4   -- # bits/X sample.
         ); 
PORT  (
       X        : IN  std_ulogic_vector(Wx-1 downto 0);
       C        : IN  fir_coefficient_type;
	 CLK      : IN  std_ulogic;
	 RESETB   : IN  std_ulogic;
	 Y        : OUT std_ulogic_vector(Wx-1 downto 0)
	);
END fir;

ARCHITECTURE behav OF fir IS
--------------------------------------------------------------
COMPONENT in_shifter_fir
GENERIC (
   	   N_taps : integer := 4;  -- # shifter's words.
	   Wx     : integer := 6   -- # bits/sample.
         ); 
PORT  (
       SI             : IN  std_ulogic_vector(Wx-1 downto 0);
	 CLK_SHIFT      : IN  std_ulogic;
	 RESETB         : IN  std_ulogic;
	 SO             : OUT fir_shifter_type
	);
END COMPONENT;

SIGNAL result : std_ulogic_vector(Wx+Wc+log2(N_taps)-1 downto 0);
SIGNAL X_shifter : fir_shifter_type;

BEGIN
--------------------------------------------------------------
X_shifter_component : in_shifter_fir
GENERIC MAP (
	       N_taps=>N_taps,
	       Wx=>Wx
            ) 
PORT MAP (
          SI=>X,
	    CLK_SHIFT=>CLK,
	    RESETB=>RESETB,
	    SO=>X_shifter
	   );
--------------------------------------------------------------
PROCESS (X_shifter,C)
VARIABLE t : integer;
BEGIN
t:=0;
FOR i IN 0 TO N_taps-1 LOOP
	t:= t + conv_integer(mult_shift_add(X_shifter(i),C(i),N_taps));
END LOOP;
result<=to_stdulogicvector(t,Wx+Wc+log2(N_taps));
END PROCESS;
--------------------------------------------------------------
PROCESS (RESETB,CLK)
BEGIN
IF (RESETB='0') THEN
	Y <= (OTHERS=>'0');
ELSIF (rising_edge(CLK)) THEN
	Y <= result(Wx-1 downto 0);
END IF;
END PROCESS;
--------------------------------------------------------------
END behav;